DRAM Buffer Chips for Signal Integrity and Capacity
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Solution Overview
Problem
The increasing interface speed of DRAMs poses challenges in signal integrity and memory capacity, as higher speeds require fewer DIMM slots to maintain clean signals, limiting maximum memory capacity and introducing latency and cost issues with Fully Buffered DIMMs (FB-DIMMs).
Innovation Solution
Stacking DRAMs on top of each other, combined with partitioning high-speed DRAMs into low-speed memory core chips and high-speed interface chips, and using buffer chips to isolate electrical loads, allows for increased memory capacity without degrading performance and reduces latency by minimizing the number of distributed loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the interface speed of DRAMs is increased, then the data transmission rate is improved, but the signal integrity deteriorates and the number of supported DIMM slots decreases
Solution Approach 1:
The patent segments the memory system into multiple independent memory channels, each capable of operating at high speeds with limited loads. By dividing the overall memory capacity across multiple channels rather than loading a single channel with many DIMMs, the system maintains signal integrity on each channel while achieving high total capacity through parallel operation of multiple channels.
2Reliability
If the number of DIMM slots per memory channel is decreased to maintain signal integrity at high speeds, then the signal quality is improved, but the maximum memory capacity is limited
Solution Approach 1:
The patent transitions from a single-dimension approach (increasing capacity by adding more DIMMs to one channel) to a multi-dimensional approach by introducing multiple independent memory channels. Each channel operates with limited loads to maintain signal integrity, while the aggregate capacity across multiple channels achieves the desired high memory capacity, effectively adding a spatial dimension (number of channels) to the system architecture.
3Quantity of substance
If Fully Buffered DIMMs are used to increase memory capacity, then the capacity is improved, but the latency increases and cost increases
Solution Approach 1:
The patent employs buffer chips as intermediaries between the memory channels and the DIMM modules. These buffer chips manage the interface between high-speed memory channels and standard-speed DIMMs, allowing the system to achieve high capacity through multiple channels without requiring expensive FB-DIMMs. The buffer chips handle protocol conversion and timing management, reducing latency compared to direct FB-DIMM connections while maintaining compatibility with standard DIMMs.
Data Source
AI summary
Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.