DRAM Tile Segmentation for Backward Compatibility and Yield
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Solution Overview
Problem
As DRAM cells shrink due to advancements in process technology, they face issues with data retention time due to increased leakage and reduced storage capacitance, leading to variability in performance and incompatibility with legacy systems that expect stringent specifications.
Innovation Solution
A method for testing and repairing memory cells to ensure they meet both relaxed and stringent performance parameters, allowing new memory devices to be compatible with legacy systems by identifying and replacing cells that fall outside specified ranges and using resources to repair them, thereby extending the write time specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk to increase capacity, then storage capacitance and transistor size are reduced, but data retention time deteriorates due to increased leakage and reduced storage capacitance
Solution Approach 1:
The memory array is divided into multiple tiles, each capable of independent testing and repair. This segmentation allows defective cells to be isolated and replaced without affecting the entire memory device, thereby maintaining data retention reliability while supporting continued scaling for higher capacity.
Solution Approach 2:
The patent implements preliminary testing of memory cells during manufacturing to identify and repair defective cells before the device is shipped. This preliminary action ensures that only cells meeting the required data retention specifications are used, maintaining reliability despite the reduced sizes caused by scaling.
2Productivity
If new memory devices with relaxed performance parameters are designed, then manufacturing yield improves, but compatibility with legacy systems deteriorates
Solution Approach 1:
The patent implements dynamic testing that adapts to different performance specifications. The testing process can operate in two modes: stringent mode for legacy system compatibility and relaxed mode for improved yield. This dynamic approach allows the same manufacturing process to serve both compatibility requirements without compromising either.
Solution Approach 2:
The patent changes the testing parameters dynamically based on the target application. By adjusting the performance thresholds and testing criteria, the system can produce memory devices that meet either legacy specifications or relaxed specifications, thereby achieving both compatibility and improved yield.
3Adaptability or versatility
If stringent performance parameters are enforced during testing, then backward compatibility with legacy systems is maintained, but manufacturing yield decreases due to more cells failing specifications
Solution Approach 1:
The memory array is segmented into tiles that can be independently tested and repaired. This allows the system to identify and replace only the defective cells in specific tiles rather than rejecting the entire array, thereby maintaining compatibility with legacy systems while improving overall manufacturing yield.
Solution Approach 2:
The patent performs preliminary testing and repair of defective cells during manufacturing before the devices are shipped to legacy systems. This preliminary action ensures that only cells meeting the required specifications are used in legacy applications, maintaining compatibility while maximizing yield by repairing rather than rejecting defective cells.
4Productivity
If relaxed performance parameters are used, then manufacturing yield improves, but compatibility with legacy systems that expect stringent specifications deteriorates
Solution Approach 1:
The testing system dynamically adjusts performance parameters based on the target application. For legacy systems, it enforces stringent specifications; for new applications, it uses relaxed specifications. This dynamic parameter adjustment allows the same manufacturing process to achieve both high yield and legacy compatibility as needed.
Solution Approach 2:
The patent implements parameter changes in the testing process to match different performance requirements. By changing the acceptance criteria and testing thresholds, the system can produce memory devices optimized for either legacy compatibility or improved yield, without compromising either objective.
Data Source
AI summary
A method for testing a memory device. The method can include coupling the memory device to a test apparatus and determining whether each of the memory cells in the memory device is within a first specification range. Each of the cells that fall outside of the first range can be identified. Each of the cells that meet the second specification range can be tested. The method can include selecting a tile associated with a highest number of cells that fall outside of the second range. A resource can then be used to repair each of the cells that fall outside of the second range for a tile associated with a fewer number of cells that fall outside of the second range such that a first number of tiles meets the first range and a second number of tiles meets the second range such that the first number the second number.