Driver IC Stacked Transistors Narrow Width High Speed
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Solution Overview
Problem
As display devices become smaller and require higher definition, there is a need for a driver IC that is both compact in size and capable of high-speed operation to manage multiple gray levels effectively.
Innovation Solution
The development of a semiconductor device with a specific configuration of transistors and wirings that allows for efficient signal processing, including p-channel and n-channel transistors arranged in a way that reduces the overall size and increases the channel width of certain transistors to enhance operation speed and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the driver IC is reduced in size to meet compact display device requirements, then the area of the driver IC is reduced, but the operation speed decreases
Solution Approach 1:
The patent transitions from conventional planar transistor arrangements to a three-dimensional stacked configuration where transistors are arranged vertically across multiple layers. This dimensional change allows the driver IC to maintain compact footprint area while providing sufficient transistor channel width and length for high-speed operation, effectively decoupling area constraints from performance requirements
Solution Approach 2:
The driver IC is divided into multiple functional layers with transistors segmented across different vertical levels. This segmentation allows independent optimization of each layer's function while maintaining overall compactness, enabling high-speed signal processing in a reduced area by distributing circuit functions across multiple stacked transistor generations
2Area of stationary object
If the driver IC is reduced in size, then the area is reduced, but the width of the driver IC increases
Solution Approach 1:
By stacking transistors vertically across multiple layers, the patent converts horizontal space requirements into vertical stacking height. This dimensional transformation allows the driver IC to achieve reduced overall area while maintaining adequate transistor dimensions, preventing excessive width expansion that would occur with conventional planar scaling
3Area of stationary object
If transistors are arranged to reduce driver IC size, then the area is reduced, but the channel width of transistors must be increased to maintain operation speed
Solution Approach 1:
The patent utilizes vertical stacking to provide additional transistor channel width in the vertical dimension without increasing horizontal footprint. This allows transistors to maintain sufficient channel dimensions for high-speed operation while the overall driver IC occupies reduced area, effectively resolving the conflict between compactness and transistor performance requirements
Data Source
AI summary
To provide a small driver IC, a driver IC with a narrow width, a driver IC capable of high-speed operation, a small semiconductor device, a semiconductor device with a narrow width, or a semiconductor device capable of high-speed operation. The semiconductor device includes first to third circuits. The first and second circuits each include transistors with a first channel width. The third circuit includes transistors with a second channel width. The second channel width is larger than the first channel width. The first circuit is configured to select one of first to 2N-th potentials (N is an integer of 1 or more). The second circuit is configured to select one of (2N+1)-th to 4N-th potentials. The third circuit is configured to select the potential selected by the first circuit or the potential selected by the second circuit. The first to third circuits are arranged in line.