Driving Circuit Preventing Shoot-Through via Dead Time Control
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Solution Overview
Problem
Conventional driving circuits experience shoot through phenomena at high frequencies due to RC delays, where the upper and lower bridge switches are simultaneously turned on, causing inefficiencies and errors in signal processing.
Innovation Solution
A driving circuit with logical signal and dead time circuits that determine the leading and trailing edges of switch signals based on pulse width modulation signals, ensuring that the upper and lower bridge switches are not activated simultaneously by confirming the off-state of one phase's switch signal before changing the other phase's signal, thereby preventing shoot through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the driving circuit operates at high frequency, then the switching speed and productivity are improved, but the RC delay causes the logical signal to change before the switch signal ends, resulting in simultaneous turn-on of upper and lower bridge switches (shoot through phenomenon)
Solution Approach 1:
The dead time circuit performs preliminary action by delaying the leading edge and truncating the trailing edge of the switch signal in advance, ensuring that the switch signal ends before the logical signal changes state. This prevents the shoot through phenomenon by proactively adjusting the timing relationship between logical and switch signals before the high frequency operation can cause synchronization issues.
2Loss of time
If the logical signal changes state immediately, then the response time is reduced, but the RC delay causes the switch signal to not end before the logical signal changes, leading to simultaneous conduction of complementary switches
Solution Approach 1:
The dead time circuit acts as an intermediary between the logical signal circuit and the switch signal output. It mediates the timing relationship by introducing controlled delays and truncations, ensuring that the switch signal maintains proper timing margins relative to the logical signal changes, thereby preventing simultaneous conduction without significantly increasing the overall response time.
3Device complexity
If no dead time control is implemented, then the device complexity is reduced, but at high frequencies the RC delay causes overlapping of switch signals and simultaneous turn-on of bridge switches
Solution Approach 1:
The dead time circuit implements preliminary action by pre-adjusting the switch signal timing characteristics (delaying leading edge, truncating trailing edge) based on anticipated high frequency operation requirements. This ensures reliable timing margins are maintained without requiring complex real-time adjustment mechanisms, thus achieving improved reliability with moderate additional circuit complexity.
Data Source
AI summary
A driving circuit and a switch signal generation method are provided. The driving circuit receives a PWM signal and provides a first switch signal and a second switch signal. The driving circuit includes a logical signal circuit, a lower bridge dead time circuit and a lower bridge driving circuit. The logical signal circuit provides a first logical signal and a second logical signal according to the PWM signal. The lower bridge dead time circuit determines a leading edge of a lower bridge dead time signal according to the first logical signal and determines a trailing edge of lower bridge dead time signal according to a trailing edge of first switch signal. The lower bridge driving circuit determines a leading edge of second switch signal according to second logical signal and determines a trailing edge of second switch signal according to the trailing edge of lower bridge dead time signal.