DRAM Erasure Circuitry for Rapid Data Randomization
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Solution Overview
Problem
Current software-based methods for erasing data from DRAM in cloud virtualization are slow and inefficient, leading to potential data privacy breaches and prolonged VM boot times due to the need for sequential memory-write operations, which are not acceptable in cloud computing contexts where quick resource allocation is critical.
Innovation Solution
A hardware-based erasure circuitry that initiates a dummy operation to randomize data in memory cells at predefined events, such as user session termination or switching, using a control unit and DRAM controller to quickly erase data before reallocating memory resources, thereby ensuring data privacy and reducing boot times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based zeroing operations are used to erase DRAM data, then data privacy is protected, but the erasure process becomes slow and extends VM boot time
Solution Approach 1:
The patent replaces software-based sequential memory-write operations with hardware-based dummy read operations. The memory controller automatically performs randomizing reads during refresh cycles, eliminating the need for CPU-intensive software loops that sequentially write zeros to each memory location. This substitution of hardware automation for software processing dramatically reduces erasure time while maintaining security.
Solution Approach 2:
The memory controller is enhanced to autonomously perform data randomization during its existing refresh operations. Instead of requiring external software intervention to erase data, the system enables the memory controller to self-service the erasure function by integrating randomization into its mandatory refresh cycle, thereby achieving continuous security maintenance without additional processing overhead.
2Loss of information
If sequential memory-write operations are performed to zero out DRAM content, then complete data erasure is achieved, but the operation becomes computationally expensive and slow
Solution Approach 1:
The patent leverages the periodic refresh cycles inherent to DRAM operation to perform data randomization. Instead of executing a single lengthy sequential write operation, the system distributes erasure actions across multiple periodic refresh intervals. Each refresh cycle performs randomizing reads on portions of memory, collectively achieving complete erasure through repeated periodic actions rather than one slow operation.
3Reliability
If software solutions are used to wipe physical memory at boot up or after termination, then data security is maintained, but resource allocation time is significantly prolonged
Solution Approach 1:
The system performs data randomization during the memory refresh process that occurs continuously in the background, rather than waiting for boot-up or termination events to trigger erasure. By preliminary integrating security actions into ongoing refresh operations, the system ensures data is continuously randomized without creating bottlenecks during critical resource allocation moments.
Data Source
AI summary
The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.