DRAM-Based Neural Network Weights via Analog Sensing
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Solution Overview
Problem
Existing artificial neural network (ANN) implementations face limitations in flexibility and scalability due to the need for physical reconfiguration or replacement of hardware when updating neural networks, particularly in applications like self-driving vehicles, where adaptability is crucial. Additionally, current memory solutions are not efficient for storing and updating the large number of weights and biases required for high-performance ANNs.
Innovation Solution
The integration of artificial neural network functionality within dynamic random-access memory (DRAM) enables a high-density, highly configurable, and reprogrammable neural network architecture. This architecture allows for user-configurable neuron connections and function selection, with data calculation performed directly within the memory device, reducing the need for external data transfer and enabling in-situ training and updating of neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-implemented ANNs are used to maintain flexibility and retrainability, then adaptability is improved, but computing performance and efficiency deteriorate
Solution Approach 1:
The patent merges the memory function (DRAM) with the computing function (neural network processing) into a single integrated system. The DRAM array simultaneously stores weight data and performs analog multiplication operations, eliminating the need to transfer data between separate memory and processing units. This integration resolves the contradiction by enabling both high adaptability (through programmable weight storage) and high computing performance (through parallel analog processing).
Solution Approach 2:
The DRAM array is designed to serve multiple functions: storing weight data, performing analog multiplication, and supporting reconfiguration for different neural network architectures. The same hardware infrastructure can be programmed to implement various neural network configurations, achieving both versatility and high-performance computing without requiring separate specialized hardware for each function.
2Adaptability or versatility
If SRAM or volatile registers are used to create programmable ANNs, then reconfigurability is improved, but device area and cost deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameters of DRAM from traditional digital refresh-based operation to analog weight storage operation. By utilizing the capacitive charge states to represent continuous weight values rather than binary digits requiring refresh, the system achieves high reconfigurability with SRAM-level flexibility while occupying only DRAM-scale area, dramatically reducing the device area required for programmable neural networks.
3Quantity of substance
If DRAM is used for high-density storage, then storage capacity is improved, but data retention and read reliability deteriorate
Solution Approach 1:
The system performs preliminary sensing and amplification of the capacitive charge states before they decay or are disturbed by read operations. By reading the weight values through the sensing circuitry that is inherently part of the DRAM structure, the system retrieves data before significant charge leakage occurs, maintaining reliability while utilizing the high storage capacity of DRAM for neural network weights.
Data Source
AI summary
Techniques are disclosed for artificial neural network functionality within dynamic random-access memory. A plurality of dynamic random-access cells is accessed within a memory block. Data within the plurality of dynamic random-access cells is sensed using a plurality of sense amplifiers associated with the plurality of dynamic random-access cells. A plurality of select lines coupled to the plurality of sense amplifiers is activated to facilitate the sensing of the data within the plurality of dynamic random-access cells, wherein the activating is a function of inputs to a layer within a neural network, and wherein a bit within the plurality of dynamic random-access cells is sensed by a first sense amplifier and a second sense amplifier within the plurality of sense amplifiers. Resulting data is provided based on the activating wherein the resulting data is a function of weights within the neural network.