Droop Detector and Dual Mode Logic for SoC Timing Errors

The patent applies dynamics by switching logic gates between static and dynamic modes based on real-time droop detection. During droop events, critical path gates switch to dynamic mode which provides faster switching characteristics to meet timing constraints, while non-critical paths remain in static mode to minimize power consumption. This dynamic reconfiguration resolves the contradiction by providing timing reliability only when and where needed.

The patent implements local quality by selectively applying dynamic mode only to critical path logic gates that are affected by droop-induced timing violations, rather than globally changing the operating mode of all logic. The droop detector identifies specific timing violations and the control logic activates dynamic mode only for the minimal necessary subset of gates, thereby satisfying timing constraints locally while maintaining low power consumption overall.

The patent replaces the mechanical/calibration-based approach with a behavioral observation approach. Instead of characterizing and calibrating detector parameters across temperature, voltage, and aging conditions, the system directly observes timing violations caused by droops and infers droop events from these observable effects. This substitution eliminates the need for extensive 3D calibration while maintaining high detection precision.

The droop detector utilizes the system's own timing behavior as the detection mechanism. By monitoring whether logic operations complete within their allocated time budgets, the detector self-calibrates through operational observation rather than requiring external calibration procedures. The system serves its own calibration needs by using its functional performance as the measurement basis.

The patent replaces the analog voltage reference and comparator-based detection system with a fully digital timing-based detection system. Instead of using precise analog voltage thresholds, the system uses digital timing measurements of logic gate operations to infer droop events. This substitution simplifies integration with standard digital CMOS logic while maintaining accurate droop detection through temporal rather than voltage-based measurements.

The timing-based detection mechanism serves multiple functions: it detects droop events, identifies affected critical paths, and provides information for dynamic mode activation. This multi-functional approach eliminates the need for separate analog reference circuits and multiple comparator stages, reducing overall device complexity while maintaining detection accuracy through the universal timing measurement approach.

The patent applies local quality by activating dynamic mode only for specific critical path logic gates that are experiencing timing violations due to droops, rather than reducing the overall system clock frequency. This localized optimization allows non-critical paths to continue operating at full speed, thereby preventing timing errors in affected paths while maintaining high system performance overall.

The patent uses dynamics by rapidly switching logic gates between static and dynamic modes in response to detected droop events. This dynamic reconfiguration provides temporary performance optimization for critical paths during droop events without requiring global clock frequency reduction, thereby preventing timing errors while minimizing impact on overall system productivity.