DSFF Scan Chain with Completion Detection for Hold-Free Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital circuits face complexity and timing inefficiencies due to the need for separate scan clock signals during testing, which complicates clock routing and optimization in integrated circuits.
Innovation Solution
A digital circuit incorporating a differential sense flip flop (DSFF) and a completion detection circuit (CDC) that eliminates the need for a separate scan clock by using a test enable input to coordinate the transfer of test inputs, allowing sequential state elements to operate asynchronously during scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate scan clock signal is used to operate the scanning mechanism during testing, then hold time violations are prevented, but clock routing complexity is significantly increased
Solution Approach 1:
The patent merges the scan clock function with the functional clock by using a single clock signal for both normal operation and scan testing. The clock enable signal selectively gates this unified clock to sequential elements during scan mode, eliminating the need for separate scan clock routing while maintaining proper timing control.
Solution Approach 2:
The clock signal is designed to serve multiple functions: it acts as the functional clock during normal operation and as the scan clock during testing. The clock enable signal provides mode-dependent gating, allowing the same clock infrastructure to support both operational modes without requiring dedicated scan clock paths.
2Reliability
If separate scan clock signals are implemented for testing, then sequential state elements can be scanned properly, but timing optimization efficiency is reduced
Solution Approach 1:
By combining scan and functional operations under a single clock system, the patent allows timing optimization tools to treat the entire circuit uniformly. This unified approach enables more efficient timing closure and optimization since there are no separate scan timing domains that would require independent analysis and optimization passes.
3Speed
If the sequential state element is triggered before the differential logical output is completed, then scanning speed is increased, but hold time violations occur
Solution Approach 1:
The completion detection circuit provides feedback about the status of the differential logical output to the clock enable logic. This feedback mechanism allows the system to automatically wait for completion before triggering the next sequential element, ensuring hold time compliance without requiring manual timing analysis or fixed conservative delays that would reduce scanning speed.
Data Source
AI summary
A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock.