Electrical Testing TRIZ Cases
- Duty-Cycle Monitoring Circuit Without a Reference Clock
A buffer-and-flip-flop circuit measures clock high and low times directly, enabling fast duty-cycle fault detection without a reference clock.
- Flip-Flop Latch Layout With Central Clock Inverter Placement
A clock inverter placed between master and slave latches shortens clock paths and reduces flip-flop power in semiconductor layouts.
- ADC Calibration Control Using Dynamic Integration Coefficients
A monitor circuit adapts ADC integration coefficients to signal conditions, speeding calibration and preventing divergence during low-signal periods.
- FPGA Robust Memory Cells for Fast Dynamic Context Switching
Majority-based robust memory cells let FPGAs switch operating modes quickly and reliably during power-up, initialization, and reconfiguration.
- Adjustable Delay Circuit for IC Speed Variation Measurement
An adjustable delay circuit quantizes IC speed shifts across conditions, avoiding critical-path monitoring while cutting area and response time.
- Ring Oscillator Skew Detection for Dynamic IC Recalibration
Counts at multiple ring-oscillator tap nodes reveal transistor skew during operation, enabling dynamic IC recalibration under changing conditions.
- Adjustable Delay Circuit for Real-Time IC Speed Monitoring
An adjustable delay path detects IC speed shifts in monitor mode, enabling faster clock tuning without complex critical path tracking.
- Optical Sensor Circuit with Shared Signal Conditioning Against Crosstalk
Shared signal conditioning and selective sensor control cut ambient-light errors and crosstalk in multi-optical sensor circuits.
- Semiconductor Timing Sensor for Dynamic Voltage and Clock Adjustment
Sensitive timing-path replicas track process and temperature variation, enabling real-time voltage and clock tuning with lower area and power overhead.
- FPGA Test Board Skew Calibration Using SerDes Strobe Signals
A SerDes-generated strobe lets an FPGA test board calibrate data-signal skew accurately without a separate IC, reducing tester size and cost.
- Flip-Flop Latch Pre-Charge Circuit for Low-Latency Switching
Pre-charging and feedback-controlled pull-down cut flip-flop data-to-output latency while lowering switching power in high-speed circuits.
- Signal Generator Non-Linearity Evaluation Using Snapshot Spectral Analysis
Amplitude-peak snapshots isolate the noisiest signal segments, speeding non-linearity evaluation and improving compensation accuracy.
- Deskew Delay Circuit Using Current Splitting for Timing Linearity
Current-splitting delay cells improve deskew timing alignment by reducing skew, midscale non-linearity, and edge placement errors in test systems.
- FPGA Logic Tile Interconnect Isolation for Parallel Test Readback
Test mode control disconnects adjacent FPGA logic tiles, enabling parallel isolation testing and readback with less test time.
- Flop Vulnerability Categorization Using Circuit Data Dependencies
Classifying flops as vulnerable, conditional, or isolated from data dependencies improves transient error assessment and circuit reliability.
- ADC Monitor Circuit for Signal-Dependent Calibration Control
A monitor circuit adjusts ADC calibration to actual signal conditions, preventing divergence on irregular inputs and shortening convergence time.
- DSFF Scan Chain with Completion Detection for Hold-Free Testing
Completion detection lets DSFF-based scan chains shift test data without a separate scan clock, avoiding hold violations and routing overhead.
- Ring Oscillator Layout for Sensitive NBTI and PBTI Detection
Alternating NAND and NOR stages with different drive powers make ring oscillators more sensitive to NBTI and PBTI degradation.
- Level-Sensitive Scan Flip-Flop for Sleep-Mode Data Retention
A master-slave flip-flop keeps data through sleep mode by using level-sensitive scan circuitry on a separate power rail without timing penalty.
- Flip-Flop Trigger Circuit With Variable Voltage Swing for Scan-Test Power
Variable trigger-stage voltage swing reduces scan-test power by limiting transistor toggling while preserving flip-flop state accuracy.
- Programmable Shift Register Load Mapping for Low-Latency Data Access
A programmable load location and bit remapper cut shift-register retrieval latency while storing varied bit combinations efficiently.