FPGA Logic Tile Interconnect Isolation for Parallel Test Readback
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Solution Overview
Problem
Current methods for testing logic tiles in field programmable gate arrays (FPGAs) are inefficient, as they often require serial testing and cannot isolate the circuitry of individual tiles from others, making it difficult to determine the integrity and operability of each tile independently.
Innovation Solution
The development of circuitry and techniques that allow for parallel testing of logic tiles, enabling the isolation of each tile's circuitry during testing by disconnecting it from other tiles and external circuitry, and the use of test mode control circuitry to configure and read-back test data, facilitating concurrent testing and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial testing is used for logic tiles, then testing can be performed with simple circuitry, but test time is excessive and productivity is low
Solution Approach 1:
The testing system is segmented into multiple independent test channels, each capable of testing a subset of logic tiles simultaneously. The logic tile array is divided into groups that can be tested in parallel through different scan chains, allowing multiple testing operations to occur concurrently rather than sequentially.
Solution Approach 2:
Multiple scan chains are merged into a unified test architecture that shares common control logic and response capture resources. The patent combines several scan chains into a single response capture register that can collect test results from multiple logic tile groups simultaneously, reducing overall system complexity while enabling parallel testing.
2Measurement precision
If logic tiles are tested in isolation from other tiles, then testing accuracy for individual tiles is improved, but device complexity increases due to isolation circuitry
Solution Approach 1:
The interconnect network dynamically reconfigures its connectivity during testing by activating specific switch settings that isolate selected logic tiles from the rest of the array. Multiplexers and switches in the interconnect network are controlled to create isolated test paths, allowing individual tile testing without permanent physical isolation circuitry.
Solution Approach 2:
The interconnect network acts as an intermediary between logic tiles during testing. By controlling the interconnect switches and multiplexers, the system mediates the connection between tested tiles and the test stimulus/response paths, enabling isolation of individual tiles through software-controlled interconnect routing rather than dedicated isolation hardware.
Data Source
AI summary
An integrated circuit comprising a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode, (2) a test mode, (3) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to electrically connect with the interconnect network of at least one adjacent logic tile of the plurality of logic tiles via one or more tile-to-tile interconnects in the normal operating mode and (4) isolation circuitry, connected between the associated interconnect network and the interconnect network of each adjacent logic tile, configurable to responsively disconnect tile-to-tile interconnects disposed between the interconnect network of each adjacent logic tile in the test mode to thereby electrically disconnect interconnect networks of adjacent logic tiles in the test mode.