Flip-Flop Trigger Circuit With Variable Voltage Swing for Scan-Test Power
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Solution Overview
Problem
Silicon-on-chip (SOC) designs face high power consumption issues during full scan testing due to simultaneous toggling of flip-flops and combinational logic, exceeding the circuit's power rating as IC chip density and speed increase.
Innovation Solution
A flip-flop circuit design that includes a trigger stage configured to set an output signal to two different voltage swings, reducing power consumption by toggling fewer transistors in response to a clock signal, with a voltage setting circuit adjusting the voltage swing based on the logical state of the latch output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all flip-flops and combinational logic are toggled simultaneously during scan testing, then test access to internal nodes is achieved, but power consumption exceeds the circuit's power rating
Solution Approach 1:
The patent applies dynamics by making the voltage swing of the trigger stage output signal variable rather than fixed. The trigger stage is configured to provide different voltage swings (first voltage swing or second voltage swing) to the second latch input signal based on the current logical state of the latches. This dynamic adjustment reduces unnecessary transistor toggling and thereby reduces power consumption during scan testing while maintaining test access capability.
2Device complexity
If the trigger stage output signal uses a fixed voltage swing, then circuit operation is simple, but unnecessary transistor toggling increases power consumption
Solution Approach 1:
The patent applies parameter changes by modifying the voltage swing parameter of the trigger stage output signal based on the logical state of the latches. When the latches are in certain states, a reduced voltage swing is applied to the second latch input signal, which minimizes transistor toggling and reduces power consumption. This parameter adjustment is achieved through additional control logic that monitors latch states and adjusts the trigger stage output accordingly, resolving the contradiction between operational simplicity and power consumption.
Data Source
AI summary
A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have different voltage swings based on the first output signal and the second output signal. The trigger circuit includes a logic circuit coupled to at least the first latch or the second latch. The logic circuit is configured to output the second output signal.