Level-Sensitive Scan Flip-Flop for Sleep-Mode Data Retention

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Solution Overview

Problem

Preserving data in processor cores during low power mode without impacting performance is challenging, as existing methods like clock gating lead to leakage and data loss due to power supply being on, and powering off results in data loss.

Innovation Solution

Implementing a flip-flop with scan circuitry and an ungated power supply rail to retain data during sleep mode, allowing data to be stored and restored without timing overhead or performance degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If clock gating is used to reduce dynamic power consumption, then power consumption is reduced, but leakage power increases and data is lost due to power supply being on

Engineering Contradiction:

Improvedynamic power consumptionVSAvoidleakage power

Core Design Contradiction:

Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The flip-flop is divided into two independent stages: master stage and slave stage, each with separate power supply control. This segmentation allows the master stage to be powered down while the slave stage retains data, resolving the contradiction between reducing dynamic power and preventing leakage-induced data loss.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Data is preliminarily transferred from the master stage to the slave stage before the master stage is powered down. This preliminary action ensures data integrity during low power mode by preserving data in the slave stage which remains powered, eliminating the data loss problem associated with complete power gating.

Inventive Principle:

Principle #10Preliminary action

2Loss of energy

If power supply is turned off to save power, then power consumption is reduced, but data is lost

Engineering Contradiction:

Improvepower consumptionVSAvoiddata

Core Design Contradiction:

Loss of energyVSLoss of information

Solution Approach 1:

The flip-flop is segmented into master and slave stages with independent power control. The slave stage remains powered while the master stage is powered down, allowing data to be preserved in the slave stage while achieving power savings in the master stage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The slave stage acts as an intermediary data storage element that receives data from the master stage before power down. This intermediary structure enables data to be preserved during low power mode by maintaining power to the slave stage while gating power to the master stage.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If additional circuitry is added to support data retention during sleep mode, then data integrity is maintained, but device complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The slave stage serves multiple functions: it acts as the output stage during normal operation and as a data retention register during low power mode. This multi-functionality eliminates the need for separate retention circuitry, maintaining data integrity without increasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The data retention function is merged with the existing slave stage of the flip-flop. By combining the retention function with the output stage, the patent avoids adding separate retention circuitry, thus maintaining data integrity while minimizing increases in device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10374584B1Low power retention flip-flop with level-sensitive scan circuitry

Publication Date: 2019.08.06 INTEL CORP

AI summary

An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.