DTC Interconnect Layout to Prevent UBM Plasma Arcing
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Solution Overview
Problem
As semiconductor devices miniaturize, issues such as plasma arcing during deposition steps for under bump metallizations (UBMs) lead to component burn-out and circuit shorts, affecting capacitor density and yield.
Innovation Solution
Incorporating doped regions in the substrate to reduce resistivity and forming specific interconnect layouts that minimize charge accumulation and voltage drops, thereby preventing arcing-induced damage to deep trench capacitors (DTCs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but plasma arcing during deposition leads to component burn-out and circuit shorts
Solution Approach 1:
A seal ring structure is introduced as an intermediary element between the substrate and the deep trench capacitor. This seal ring acts as a protective mediator that prevents plasma arcing from directly reaching and damaging the capacitor components during UBM deposition, thereby maintaining component reliability while enabling continued miniaturization for higher integration density.
Solution Approach 2:
The seal ring structure is formed in advance before the UBM deposition process. By preliminarily establishing this protective structure, the design prevents plasma arcing damage before it can occur during subsequent deposition steps, allowing the system to maintain reliability throughout the manufacturing process while achieving higher integration density through reduced feature sizes.
2Quantity of substance
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but charge accumulation and voltage drops increase causing arcing-induced damage
Solution Approach 1:
The seal ring structure serves as a protective intermediary that mitigates the harmful effects of charge accumulation and voltage drops. By positioning this conductive structure between the substrate and the capacitor, it provides a controlled path for charge dissipation and reduces voltage potential differences, thereby preventing plasma arcing while maintaining high capacitor density through miniaturization.
Solution Approach 2:
The seal ring structure is designed to create equipotential regions that reduce voltage drops across the substrate. By establishing conductive pathways that equalize potential differences, the seal ring minimizes the voltage gradients that lead to plasma arcing, enabling higher capacitor density without suffering from arcing-induced damage.
3Ease of manufacture
If deposition process is performed for UBM formation, then under bump metallization is created, but plasma arcing causes burn-out and circuit shorts in DTCs
Solution Approach 1:
The seal ring structure functions as a protective intermediary during the UBM deposition process. It shields the deep trench capacitor from direct exposure to plasma arcing while allowing the UBM formation process to proceed normally, thus maintaining both ease of manufacture and device reliability.
Solution Approach 2:
The seal ring structure is formed beforehand to provide protective cushioning against plasma arcing during UBM deposition. This preliminary protective measure absorbs or redirects the harmful plasma energy before it can reach the vulnerable capacitor components, ensuring their integrity throughout the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents burn-out and shorts in DTCs by reducing resistivity and charge accumulation, enhancing capacitor density and improving semiconductor device yield.
Implementation Method 1
Incorporating doped regions in the substrate to reduce resistivity
Implementation Method 2
a conductive line electrically coupling the seal ring structure to the first conductive via
Implementation Method 3
deposition steps for under bump metallizations (UBMs)
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.