Dual-Antifuse Memory Cell Layout for Short-Free OTP Reading

Solution Overview

Problem

Conventional OTP memory cells, including dual-antifuse devices, face reliability issues due to potential shorts within the array, leading to unreliable reading and programming operations.

Innovation Solution

A memory cell design incorporating a dual-antifuse device with a first and second antifuse connected to a common terminal and a first and second pass-gate transistor, arranged in rows and columns, allowing selective and individual programming and reading operations without IR drops due to shorts, using specific wordline and bitline bias conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If dual-antifuse devices are used to store two bits of data, then memory structure area is reduced, but reading and programming operations become less reliable due to potential shorts within the array

Engineering Contradiction:

Improvememory structure areaVSAvoidreading and programming operation reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The memory cell is segmented into two independent antifuse devices (first and second antifuses), each with separate bitline connections. This segmentation allows individual programming and reading of each antifuse, preventing interference between them and eliminating the reliability issues caused by shorts in shared-path configurations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Pass-gate transistors are introduced as intermediary elements between the bitlines and the antifuse devices. These pass-gates act as controlled switches that enable selective programming and reading operations, isolating the antifuses from direct bitline connections and preventing short-circuit effects from propagating through the array.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of stationary object

If conventional dual-antifuse devices are used, then area consumption is reduced, but shorts within the array cause unreliable operation results

Engineering Contradiction:

Improvearea consumptionVSAvoidshorts within the array

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The memory cell is segmented into two independent antifuse devices (first and second antifuses), each with separate bitline connections. This segmentation allows individual programming and reading of each antifuse, preventing interference between them and eliminating the reliability issues caused by shorts in shared-path configurations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Pass-gate transistors are introduced as intermediary elements between the bitlines and the antifuse devices. These pass-gates act as controlled switches that enable selective programming and reading operations, isolating the antifuses from direct bitline connections and preventing short-circuit effects from propagating through the array.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20260047085A1Memory cell including dual-antifuse device, memory structure, and operating method

Publication Date: 2026.02.12 GLOBALFOUNDRIES US INC

AI summary

Disclosed is a memory cell including a dual-antifuse device between a first pass-gate transistor and a second pass-gate transistor. The dual-antifuse device includes first and second antifuses having a common terminal and each also having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between a first bitline and the additional terminal of the first pass-gate transistor. The second pass-gate transistor is connected between a second bitline and the additional terminal of the second pass-gate transistor. The common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a wordline. Also disclosed is a memory structure including an array of such memory cells and an associated operating method. Within the array, different wordline and bitline bias conditions can be employed in order to reliably perform programming or read operations of a selected antifuse in a selected cell.