Mode-Specific Bias Circuits for Power Amplifier Linearity
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Solution Overview
Problem
Existing power amplifier circuits in wireless communication terminals face issues with gain compression, adjacent channel leakage power ratio (ACLR) deterioration, and decreased linearity when switching between low and high output power modes due to the use of a bias circuit that applies bias to amplifying transistors in both modes.
Innovation Solution
A power amplifier circuit design that includes a first amplifier for low power mode, a second amplifier for high power mode, and separate bias circuits for each mode, utilizing emitter follower and feedback type bias circuits to individually control the amplifiers, ensuring optimal operation and linearity across power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bias circuit is used to apply bias to the amplifying transistor in both low power mode and high power mode, then the device complexity is reduced, but gain compression occurs, ACLR deteriorates, and linearity decreases
Solution Approach 1:
The single bias circuit is segmented into two separate bias circuits: a first bias circuit for low power mode and a second bias circuit for high power mode. Each bias circuit is independently configured to provide optimal bias conditions for its specific power mode, thereby preventing gain compression and maintaining linearity in both operating conditions without excessive complexity increase.
Solution Approach 2:
The bias circuit configuration is made dynamic by switching between the first bias circuit and the second bias circuit based on the power mode. The switching mechanism allows the system to adapt the bias conditions according to the current operating state (low power or high power), ensuring optimal performance and linearity across different power levels.
2Device complexity
If a single bias circuit is used for both power modes, then the device complexity is reduced, but ACLR deteriorates
Solution Approach 1:
The bias circuit is segmented into mode-specific circuits where the first bias circuit optimizes bias for low power mode and the second bias circuit optimizes bias for high power mode. This segmentation ensures that each circuit is tuned to minimize ACLR for its specific operating condition, preventing the ACLR deterioration that occurs with a single generic bias circuit.
Solution Approach 2:
Each bias circuit is designed with local quality optimized for its specific power mode. The first bias circuit has parameters optimized for low power operation while the second bias circuit has parameters optimized for high power operation. This local optimization ensures that ACLR is minimized in each specific operating condition rather than compromising both modes with a single circuit design.
3Device complexity
If a single bias circuit is used for both power modes, then the device complexity is reduced, but gain compression occurs
Solution Approach 1:
The bias circuit is segmented into two independent circuits that can be selectively activated based on power mode. The first bias circuit provides appropriate bias conditions for low power mode while the second bias circuit provides optimized bias for high power mode, preventing gain compression that would occur with a single circuit operating outside its optimal range.
Solution Approach 2:
The bias circuit parameters are changed according to power mode by switching between the first and second bias circuits. Each circuit is designed with specific parameter values (such as bias currents and voltages) optimized for its target power mode, allowing the system to maintain linear operation and prevent gain compression across the full power range without requiring a single complex circuit with adjustable parameters.
Data Source
AI summary
A power amplifier circuit includes first and second bias circuits to each apply a bias to first and second amplifiers in first and second modes, respectively. The first bias circuit includes: a first transistor having a collector connected to a power supply electric potential, an emitter connected to the first amplifier, and a base connected to a current source; and a second transistor and a third transistor being diode-connected and connected between the base of the first transistor and a reference electric potential. The second bias circuit includes: a fourth transistor having a collector connected to a power supply electric potential, an emitter connected to the second amplifier, and a base connected to a current source; and a fifth transistor having a base connected to the emitter of the fourth transistor, a collector connected to the base of the fourth transistor, and an emitter connected to a reference electric potential.