Dual Capping Layer Structure for Semiconductor Contact Resistance
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Solution Overview
Problem
In semiconductor integrated circuit devices, the increasing number of stacked memory cells leads to challenges in securing cell current due to high contact resistance between the channel region and the bit line region, primarily caused by high contact resistance between the channel layer and metal wiring, which is exacerbated by the presence of seams in the capping layers.
Innovation Solution
The solution involves forming a first capping layer with higher impurity concentration and grain size, followed by etching it back to create a recess for a second capping layer with lower resistance, which is grown using the first capping layer and channel layer as a seed, allowing direct contact with metal wiring and reducing seam-induced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to achieve high integration, then the integration degree is improved, but the contact resistance between channel region and bit line region increases
Solution Approach 1:
The capping layer is divided into two distinct layers: a first capping layer with higher impurity concentration and larger grain size, and a second capping layer with lower impurity concentration and smaller grain size. This segmentation allows each layer to perform its specific function - the first layer provides low resistance contact while the second layer serves as a seed layer for metal wiring growth, thereby resolving the contradiction between high integration and low contact resistance.
Solution Approach 2:
Different regions of the capping structure are assigned different properties - the first capping layer positioned at the channel region interface has higher impurity concentration and larger grain size for low resistance, while the second capping layer positioned at the metal wiring interface has lower impurity concentration for better seed layer performance. This local differentiation optimizes both contact resistance and wiring formation.
2Device complexity
If a single capping layer is used, then the device structure is simple, but the contact resistance is high due to seam formation
Solution Approach 1:
The capping layer is segmented into two layers with different impurity concentrations and grain sizes. The first capping layer with higher impurity concentration and larger grain size prevents seam formation and reduces contact resistance, while the second capping layer provides a suitable seed layer for metal wiring. This segmentation resolves the contradiction between structural simplicity and low contact resistance.
Solution Approach 2:
The capping structure uses a composite of two layers with different material properties - the first layer has higher impurity concentration and larger grain size for low resistance contact, while the second layer has lower impurity concentration for optimal seed layer characteristics. This composite structure eliminates seams and reduces overall contact resistance while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves contact resistance by diffusing impurities into the second capping layer, increasing its grain size and reducing specific resistance, thereby lowering the overall contact resistance and preventing seam-related high wiring resistance in semiconductor integrated circuit devices.
Implementation Method 1
improves contact resistance by diffusing impurities into the second capping layer, increasing its grain size and reducing specific resistance
Data Source
AI summary
A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.