Dual-Channel Transistor Structure for Drive Current Scaling
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Solution Overview
Problem
Conventional multi-gate transistors, such as MBC transistors, face challenges in achieving satisfactory drive current as the scaling down process continues, limiting their performance in high-density semiconductor integrated circuits.
Innovation Solution
The implementation of a dual-channel transistor (DCT) structure, where a first channel layer formed of silicon or other semiconductors is combined with a second channel layer made of a two-dimensional (2D) material, such as graphene or transition metal dichalcogenides, to enhance drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor structures (MBC, FinFET) are used to improve gate control and reduce leakage, then off-state current and short-channel effects are reduced, but drive current becomes insufficient at scaled dimensions
Solution Approach 1:
The channel is segmented into multiple independent channel layers (first channel layer and second channel layer) stacked vertically. Each layer can independently conduct current, effectively multiplying the drive current capability while maintaining the same footprint area. The gate structure controls each segment independently, preserving gate control effectiveness.
Solution Approach 2:
The channel structure transitions from a two-dimensional planar configuration to a three-dimensional stacked configuration. By adding the vertical dimension with multiple channel layers, the effective channel width is increased without increasing the lateral footprint, thereby enhancing drive current while maintaining scaled dimensions.
2Device complexity
If conventional single-channel structures are used, then device structure is simple, but effective channel width and on-state current are limited
Solution Approach 1:
The channel structure utilizes the vertical dimension by stacking multiple channel layers. This increases the effective channel width (area available for current flow) without increasing the lateral footprint area, effectively adding dimensionality to overcome the limitations of planar scaling.
Solution Approach 2:
Multiple channel layers are nested vertically within each other, forming a stacked configuration. The first channel layer and second channel layer are positioned one above the other, sharing the same lateral footprint but providing additive current conduction paths, similar to nested dolls occupying the same space.
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.