Nanoinformatics TRIZ Cases

An overlap imprinting technique confines polymerizable material between adjacent fields, preventing extrusions that disrupt residual layer thickness.

Soft stamping forms UV-cured photoresist patterns on photovoltaic cells, enabling low-temperature aluminum sintering that prevents solar efficiency degradation.

A spatial light modulator system splits and combines offset images to control actinic radiation distribution during film curing.

Field focusing features control conductive filament formation to resolve inconsistent resistive measurements across ReRAM arrays.

Chiral monolayers on semiconductor substrates filter electrons to produce spin-polarized currents, eliminating complex vacuum systems and magnetic components.

Axially graded vertical nanowire transistors resolve lateral fabrication limits by varying source-drain materials to boost drive current and reduce leakage.

Radial electric field distribution in a GaN nanowire heterojunction eliminates edge concentration, raising breakdown voltage.

Anti-punch-through semiconductor layer fills recess below fin top surface to reduce leakage current in integrated circuit devices.

Using nanoribbon stacks as dual electrodes embeds capacitors near transistors, reducing area and process steps.

Systematically varying PES offset segment downtrack length encodes track position, resolving poor track ID reading accuracy in self-assembled patterned media.

Segmented microneedles create skin pathways to resolve manufacturing complexity and mechanical integrity trade-offs in transdermal delivery.

An EUVL mask fabrication method uses charged particle irradiation with halogenated xenon gas to etch the absorption layer.

Segmenting germanium into discrete islands on a sacrificial template eliminates dislocation propagation while maintaining high photo-detection capability.

Single-wall carbon nanotube back contact layer provides low potential energy barrier for electrical current flow in photovoltaic cells.

Epitaxial growth enlarges drain regions in vertical gate all around transistors, reducing parasitic capacitances and contact resistance.

Intersecting electrode patterns form pixels that enable independent photocurrent reading without external selector switches, simplifying manufacturing.

A fin-type semiconductor device uses segmented gate electrodes to control nano-sheet channels and reduce parasitic capacitance.

A photonic multiplexer shifts photons across channels to combine outputs from multiple single-photon sources.

Remote radical treatment trims gate spacer portions, reducing source/drain contact opening aspect ratio and eliminating voids.

Asymmetric reflectors redirect ultraviolet radiation to generate a uniform irradiance pattern, resolving non-uniform film curing and reducing processing time.

A vertical field effect transistor uses semiconducting carbon nanotubes grown within a porous anodic alumina template to establish surround gates.

Active element machine executes multiple instructions simultaneously by distributing computational tasks across independent active elements.

A roller nanoimprint apparatus uses an inflatable elastic film to support a mold roller, ensuring uniform pressure during pattern transfer.

Hydrogen gas-doped solvents suppress metal oxidation during self-assembled monolayer formation, ensuring uniform organic layers within nano-gaps.

A zinc oxide hole blocking layer forms via low temperature drying of a liquid composition containing bis(acetylacetonato)zinc and acetylacetone.

Segmenting transistor channels via sacrificial layers reduces off-state leakage while maintaining high operating speed.

A dual-channel transistor structure stacks a two-dimensional material layer over a semiconductor channel to increase effective channel width.

A photo-curable composition uses a fluorine-containing surfactant to form an interfacial thin film during UV curing.

Cryptographic scrambling of the master template prevents unauthorized replication while maintaining manufacturing efficiency and disk drive operability.

A reflective exposure mask integrates a low-reflective contamination inspection pattern alongside the primary reflective region.

Novel neutral layer compositions enable precise microdomain alignment in directed self-assembling block copolymers.

A calculation system adjusts resist coating distribution based on actual template pattern data to ensure accurate filling.

Non-uniform doping in a vertical MOSFET channel reduces gate-induced drain leakage, resolving the trade-off between integration density and device performance.

Segmenting the buffer, barrier, and channel layers decouples stress from band offset to enhance carrier mobility without inducing defects.

Nested top gates enhance spatial localization of quantum dots while managing device complexity for scalable quantum computing integration.

A static random access memory bit cell uses stacked transistors connected to power tracks above and below the structure.

Single-run laser exposure writes patterns and alignment marks on one substrate, ensuring high relative positional accuracy between masks.

A multibit electro-mechanical memory device unifies the attractive electrode and FET sensor into a single gate structure to reduce cantilever length.

Bit registering layer records defective cell status to reduce redundancy circuit area and improve nanometer-scale memory yield.

Transfer printing a purified carbon nanotube layer resolves dispersion aggregation and impurity issues in thin film transistor manufacturing.

Optical measuring unit determines gas concentration between mold and substrate, resolving complexity trade-offs in resin filling.

A wire-last integration technique forms suspended nanowire channels on SOI wafers using dummy gate removal and replacement gate filling.

Segmented diaphragm flexures in series or parallel configurations resolve pitch and roll misalignment to ensure uniform feature dimensions.

Selective epitaxial growth attaches nanowires to silicon-on-insulator layers, resolving in-situ doping variability through segmentation.

A damascene gate process integrates nanosized charge traps into memory cells using chaperonin protein templates for uniform distribution.

Silicon-germanium alloy nanowires with oxide shells reduce off-state leakage current while maintaining high carrier mobility.

Boron-doped diamond nanowires measure strain with high precision while resisting temperature-induced errors common in silicon sensors.

A self-aligned split gate memory structure uses spacer and in-laid formation to define gates without tight alignment tolerances.