SRAM Bit Cell With Stacked Transistors and Dielectric Walls
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Solution Overview
Problem
The development of vertically stacked semiconductor devices for SRAM bit cells faces challenges in forming efficient electrical interconnection structures, particularly with reduced cell area, where vertical interconnects are difficult to precision-form due to limited space and risk of electrical shorts, especially when scaling down to smaller dimensions.
Innovation Solution
The bit cell design incorporates power supplies arranged above and below the cell, with upper and lower transistors connected accordingly, reducing the need for extensive vertical interconnects and utilizing dielectric walls to separate gate electrodes, allowing for tighter spacing between channel tracks and improved precision in interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertically stacked transistor design is used to reduce cell area, then area efficiency is improved, but manufacturing precision deteriorates due to difficulty in forming vertical interconnects with reduced spacing
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacked architecture, arranging transistor channels at different vertical levels (first level and second level). Power supply tracks are positioned above and below the bit cell, connected via vertical interconnects that extend through the stacked structure. This dimensional change enables area reduction while managing interconnect complexity through structured vertical pathways.
Solution Approach 2:
The bit cell is segmented into distinct vertical layers with lower transistors at a first level and upper transistors at a second level. Power supply connections are segmented into separate tracks: first power supply tracks extending in a first direction and second power supply tracks extending in a second direction. This segmentation organizes the complex interconnect structure into manageable segments, improving manufacturability.
2Area of moving object
If cell area is reduced to enable denser circuits, then area efficiency is improved, but reliability deteriorates due to increased risk of electrical shorts in vertical interconnects
Solution Approach 1:
Dielectric walls are introduced as intermediary structures between adjacent channel tracks at different vertical levels. These dielectric barriers physically separate the conductive elements, preventing direct contact and electrical shorts while allowing the channels to be positioned closer together. This intermediary structure enables reduced spacing without compromising reliability.
Solution Approach 2:
By stacking transistor channels vertically at different levels rather than arranging them in-plane, the patent reduces the horizontal spacing requirements between channels. The vertical separation provided by multiple levels, combined with dielectric walls, maintains electrical isolation while enabling tighter overall cell packing and reduced area.
3Area of moving object
If channel track spacing is reduced to improve density, then area efficiency is improved, but manufacturing precision deteriorates due to difficulty in precision-forming vertical interconnects
Solution Approach 1:
Dielectric walls are formed to extend between channel tracks, providing self-aligned separation structures that define the spacing between adjacent channels. These dielectric barriers serve as built-in guides and spacers that facilitate the formation of vertical interconnects by pre-establishing the geometric boundaries, thereby improving manufacturing precision without requiring additional complex alignment steps.
Solution Approach 2:
Dielectric walls act as intermediary structures that mediate the spacing between channel tracks. By introducing these dielectric barriers, the patent enables reduced channel track spacing while maintaining manufacturability, as the dielectric walls provide physical boundaries that guide interconnect formation and ensure consistent spacing during fabrication.
Data Source
AI summary
A bit cell for a Static Random-Access Memory (SRAM) is provided that includes first and second sets of transistors. Each set of transistors includes a respective pass-gate transistor and a respectively stacked complementary transistor pair of an upper transistor and a lower transistor. A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor.