Multibit Electro-Mechanical Memory Device Cantilever Integration
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Solution Overview
Problem
Conventional memory devices face limitations in integration and data storage capacity due to parallel arrangement of cantilever electrode supporters and FET sensors, requiring long cantilever electrodes and separate configuration of attractive and FET sensors, which restricts the ability to store multibit data.
Innovation Solution
A multibit electro-mechanical memory device is developed with cantilever electrodes and bit lines formed in the same direction, reducing electrode length and unifying the attractive electrode with the FET sensor, allowing for increased integration and storage of 2 bits or more per unit cell by using a trap site structure with silicon oxide and nitride layers and interlayer insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cantilever electrode supporter and FET sensor are formed in parallel, then the device structure is conventional and easy to manufacture, but the integration is reduced and device area increases
Solution Approach 1:
The patent merges the attractive electrode and FET sensor into a unified structure where the gate electrode of the FET serves as the attractive electrode. This integration eliminates the need for separate parallel components, reducing the overall device area while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
The patent transitions from a planar parallel arrangement to a vertical stacked configuration. The cantilever electrode is positioned above the gate electrode in the vertical dimension, allowing both components to coexist in the same footprint area, thereby increasing integration density without complicating the manufacturing process.
2Reliability
If cantilever electrode is positioned away from attractive electrode and FET sensor, then the electrode can operate independently, but the electrode length increases and integration is reduced
Solution Approach 1:
The patent positions the cantilever electrode in the vertical dimension above the gate electrode rather than extending it horizontally. This spatial reconfiguration reduces the electrode length in the planar direction while maintaining operational independence through vertical separation and electrical isolation mechanisms.
3Device complexity
If separate attractive electrode and FET sensor are used, then the device structure is simple, but multibit data storage capability is limited
Solution Approach 1:
The patent combines the attractive electrode function with the FET gate electrode, creating a unified structure that enables multibit storage. The merged structure allows multiple cantilever electrodes to be associated with a single gate electrode, facilitating the storage of 2 bits or more per unit cell while maintaining relatively simple device architecture.
Solution Approach 2:
The gate electrode serves multiple functions: it acts as the attractive electrode for cantilever actuation, the control electrode for the FET, and the reference for charge trapping. This multi-functionality enables enhanced data storage capacity without proportionally increasing device complexity.
4Reliability
If long cantilever electrode is used, then the electrode can reach the attractive electrode, but the integration is reduced and device area increases
Solution Approach 1:
The patent reduces cantilever electrode length by positioning the attractive electrode vertically beneath it rather than horizontally adjacent. This vertical arrangement allows the cantilever to be shorter while still achieving reliable connection and actuation, thereby reducing the overall device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances memory device integration and data storage capacity by reducing electrode length and unifying electrical contacts, enabling efficient programming and reading of multiple bits per unit cell while maintaining a nonvolatile memory state.
Implementation Method 1
curved in a third direction vertical to the first and second direction by an electrical field induced by a first charge applied to the lower word line
Implementation Method 2
an upper word line stacked on the first and second trap sites, to which a second charge is applied to curve the first and second cantilever electrodes in a direction of the first and second trap sites
Implementation Method 3
a trap site expending in the second direction and suspended over the cantilever electrode with an upper void therebetween
Data Source
AI summary
A multibit electro-mechanical memory device and a method of manufacturing the same include a substrate, a bit line in a first direction on the substrate, a lower word line in a second direction intersecting the first direction, a pad electrode isolated from a sidewall of the lower word line and connected to the bit line, a cantilever electrode expending in the first direction over the lower word line with a lower void therebetween, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a trap site expending in the second direction over the cantilever electrode with an upper void therebetween, and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, and on the trap site.