Vertical MOSFET With Non-Uniform Doping to Suppress GIDL

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Solution Overview

Problem

The miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) faces challenges in increasing integration density and enhancing device performance due to structural limitations, particularly in reducing gate-induced drain leakage (GIDL), which is exacerbated by large negative bias voltages.

Innovation Solution

A MOSFET with a vertical channel portion and non-uniform doping concentration distribution, where the threshold voltage of one portion is lower or higher than adjacent portions, is implemented to suppress GIDL, achieved through a manufacturing process involving epitaxial growth and selective doping of sublayers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional MOSFET structures are used for miniaturization, then integration density can be increased, but device performance deteriorates due to structural limitations and increased GIDL

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by creating non-uniform doping concentration distribution within the channel portion. Specifically, the channel has different doping concentrations at different locations (higher near source/drain regions, lower in the middle), allowing different regions to have optimized characteristics: high doping near contacts for low resistance and low doping in the middle for reduced GIDL and improved mobility, thus resolving the contradiction between integration density and device performance

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If channel portion is miniaturized to increase integration density, then more devices can be integrated, but control over threshold voltage and GIDL becomes difficult

Engineering Contradiction:
Improveintegration densityVSAvoidthreshold voltage control
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

The patent applies local quality by implementing spatially varying doping concentrations in the miniaturized channel. Different regions of the channel have optimized doping levels: higher concentration near source/drain for carrier injection and lower concentration in the channel middle for reduced GIDL and improved threshold voltage control, enabling effective control in miniaturized structures

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies dimensionality change by transitioning from a conventional planar channel to a vertical channel structure with depth variation. The channel extends vertically with doping concentration varying along the depth direction, adding a new dimension for controlling electrical characteristics while maintaining small footprint for high integration density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The non-uniform doping MOSFET effectively reduces GIDL by adjusting threshold voltages, enhancing device performance and integration density while maintaining control over channel size and gate length.

Implementation Method 1

driving a dopant in the second sublayer into the channel layer in the first direction

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

providing a stack of a first material layer, a second material layer and a third material layer on a substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20230178609A1Mosfet for suppressing GIDL, method for manufacturing mosfet, and electronic apparatus including mosfet
Publication Date: 2023.06.08 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US20230178609A1 patent drawing
  • US20230178609A1 patent drawing
  • US20230178609A1 patent drawing

AI summary

A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.