Semiconductor Memory Bit Registering Layer for Defect Management
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Solution Overview
Problem
In semiconductor memory devices, the use of redundancy circuits to address defective memory cells increases chip area and testing complexity, making them inefficient for nanometer-scale memory devices with high defective bit rates, where traditional methods fail to maintain yield as block size increases.
Innovation Solution
A semiconductor memory device with a bit registering layer that records status information on each memory cell, using one-time programmable bit registers to indicate defective cells, allowing for selective access and reducing the need for redundancy cells, thereby minimizing unnecessary area usage and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy circuits are used to repair defective cells, then yield is improved, but chip area increases and testing complexity increases
Solution Approach 1:
The patent divides the memory block into smaller sub-blocks, allowing defective cells to be localized and managed at a finer granularity. This segmentation enables more efficient use of redundancy resources and reduces the overall chip area required for redundancy circuits compared to traditional full-block redundancy approaches.
Solution Approach 2:
The patent introduces a new dimension for managing defects by implementing redundancy at the sub-block level rather than at the full block level. This dimensional change in the organization of redundancy resources allows for more compact chip area utilization while maintaining yield improvement.
2Reliability
If redundancy circuits are used to repair defective cells, then yield is improved, but testing complexity increases
Solution Approach 1:
By segmenting the memory into sub-blocks with individual redundancy circuits, the testing process can be divided into smaller, more manageable units. This reduces the overall testing complexity compared to testing entire large blocks, as defects can be identified and handled at the sub-block level.
Solution Approach 2:
The patent applies redundancy and testing only to sub-blocks that contain defective cells, rather than uniformly testing and applying redundancy to all blocks. This partial action approach reduces overall testing complexity while still achieving yield improvement through targeted defect repair.
3Productivity
If block size is increased, then manufacturing efficiency is improved, but yield decreases due to high defective bit rates in nanometer-scale devices
Solution Approach 1:
The patent segments large memory blocks into smaller sub-blocks, allowing manufacturing to proceed efficiently with larger overall structures while managing defects at a smaller sub-block level. This maintains manufacturing efficiency while preventing yield degradation from high defective bit rates in nanometer-scale devices.
Solution Approach 2:
The patent applies different quality management approaches to different sub-blocks based on their defect characteristics. By managing each sub-block locally with appropriate redundancy resources, the system maintains high yield even as overall device size and manufacturing complexity increase.
Data Source
AI summary
The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a carbon nanotube memory, an atomic memory, a single electron memory, or a memory fabricated by a chemical bottom-up method, etc.