Quantum Wire Transistor Channel Segmentation for Leakage Control
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Solution Overview
Problem
Conventional transistor structures face challenges in achieving improved operating speed and integration density while minimizing short channel effects and off-state leakage, which are incompatible with enhanced performance in integrated circuits.
Innovation Solution
The development of a microelectronic device featuring optimized quantum wires that form transistor channels with improved electric performance and compactness, fabricated through a method involving the formation of thin layers and selective growth of semiconductor materials to create cylindrical or substantially cylindrical wires with specific shapes and compositions, allowing for enhanced control over channel conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase operating speed and integration density, then operating speed and integration density are improved, but short channel effects and off-state leakage increase
Solution Approach 1:
The channel is divided into multiple segments by introducing sacrificial layers at different heights, creating a multi-level structure that segments the channel region. This segmentation allows for better control of short channel effects while maintaining compactness and high integration density
Solution Approach 2:
The invention transitions from a planar channel structure to a three-dimensional multi-level channel structure by stacking sacrificial layers at different heights. This dimensional change enables improved channel control and reduced leakage while maintaining small footprint for high integration density
2Speed
If transistor size is reduced to increase operating speed, then operating speed is improved, but short channel effects increase
Solution Approach 1:
The channel is divided into multiple segments by introducing sacrificial layers at different heights, creating a multi-level structure that segments the channel region. This segmentation allows for better control of short channel effects while maintaining compactness and high integration density
Solution Approach 2:
Sacrificial layers are introduced as intermediary structures during fabrication that enable the formation of multi-level channels. These intermediary structures facilitate better gate control over the channel while maintaining short channel length for high operating speed
3Ease of manufacture
If conventional transistor structures are used to simplify fabrication, then ease of manufacture is maintained, but integration density and channel control are limited
Solution Approach 1:
Sacrificial layers are pre-formed at different heights within the channel region before final channel formation. This preliminary action enables the subsequent creation of multi-level channels with improved control and higher integration density while using standard fabrication processes
Solution Approach 2:
The invention changes the structural parameters of the channel by introducing multi-level configurations with sacrificial layers at different heights and thicknesses. This parameter change enables improved integration density and channel control while maintaining compatibility with conventional fabrication methods
Data Source
AI summary
A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.