Nanosheet Transistor Anti-Punch-Through Layer Design
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Solution Overview
Problem
As integrated circuit devices shrink in size, they face challenges with short channel effects and punch-through issues that degrade electrical characteristics, particularly in horizontal nanosheet field-effect transistors (hNSFETs), where planar transistors at lower levels are susceptible to short channel effects and punch-through, leading to increased leakage current and junction capacitance.
Innovation Solution
The integration of an anti-punch-through semiconductor layer with a different material than the source/drain region, formed in a recess below the fin top surface, which fills the anti-punch-through recess and contacts the side wall of the nanosheet, effectively reducing punch-through and leakage current by increasing the channel length and maintaining good electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased and device size is reduced, then more transistors can be packed on the substrate, but short channel effects and punch-through occur leading to increased leakage current and degraded electrical characteristics
Solution Approach 1:
The channel region is segmented into multiple horizontal nanosheets stacked vertically, creating a multi-layered channel structure. This segmentation allows the channel to be divided into discrete conducting layers, improving gate control and reducing short channel effects while maintaining high integration density.
Solution Approach 2:
The invention transitions from a planar two-dimensional channel to a three-dimensional stacked nanosheet structure. By adding the vertical dimension, multiple channel regions are packed within the same footprint area, increasing device integration while the gate wraps around each nanosheet to provide superior electrostatic control.
Solution Approach 3:
An anti-punch-through semiconductor layer is introduced as an intermediary structure between the source/drain region and the channel. This intermediate layer, positioned at the bottom of the channel, prevents carrier punch-through from source to drain while maintaining proper electrical characteristics.
2Ease of manufacture
If planar transistors are used at lower levels of the nanosheet stack, then manufacturing is simplified, but the transistors are susceptible to short channel effects and punch-through
Solution Approach 1:
Different regions of the transistor structure are given different properties: the lowermost channel level uses a planar configuration for manufacturing ease, while the upper levels use fully surrounded gate structures. The anti-punch-through layer is locally positioned at the bottom channel to provide targeted protection against punch-through effects where they occur most.
3Object-affected harmful factors
If the channel length is increased to prevent punch-through, then leakage current is reduced, but the device area increases
Solution Approach 1:
Instead of increasing channel length in the horizontal plane, the invention stacks multiple nanosheet channels vertically. This uses the vertical dimension to provide additional channel control and increase effective channel length without expanding the horizontal device footprint, thereby reducing leakage current while maintaining compact area.
Data Source
AI summary
An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.