Nanocrystal Memory Cells Using Damascene Gate and Chaperonin Templates
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Solution Overview
Problem
The integration of nanocrystals into nonvolatile memory cells is challenging due to incompatibility with high-temperature annealing processes, particularly when using metallic materials, which affects the homogeneous distribution and retention of charge trapping units.
Innovation Solution
The use of damascene gate methods and a dummy spacer to facilitate the incorporation of nanosized charge traps, allowing for high-temperature dopant anneal prior to nanocrystal deposition, and the employment of chaperonin proteins to achieve uniform distribution of nanocrystals, enabling the formation of high-density nanocrystal arrays compatible with existing semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is performed for dopant activation, then dopant activation is improved, but nanocrystal retention and homogeneous distribution deteriorate
Solution Approach 1:
The patent applies preliminary action by performing dopant activation annealing before nanocrystal formation. The process sequence is: (1) deposit sacrificial material and form patterned structures, (2) perform high-temperature dopant activation annealing (900-1100°C) to activate dopants in source/drain extensions, (3) then deposit nanocrystal charge trapping units in the opened regions. This preliminary dopant activation ensures complete dopant activation while protecting nanocrystals from thermal damage, as the nanocrystals are formed after the high-temperature step.
2Quantity of substance
If conventional nanocrystal deposition methods are used, then nanocrystal formation is achieved, but homogeneous distribution and high density are not attained
Solution Approach 1:
The patent uses sacrificial material as an intermediary to achieve homogeneous nanocrystal distribution. The process involves: (1) depositing sacrificial material (e.g., silicon oxide, silicon nitride) over the channel region, (2) patterning the sacrificial material to define regions where nanocrystals will be deposited, (3) depositing nanocrystal charge trapping units that conformally coat the sacrificial material surfaces, (4) removing the sacrificial material to leave uniformly distributed nanocrystals. The sacrificial material acts as a template that ensures uniform spacing and homogeneous distribution of nanocrystals throughout the channel region.
3Ease of manufacture
If gaps exist between source/drain extensions and gates, then fabrication is simpler, but on-resistance increases
Solution Approach 1:
The patent applies preliminary action by forming source/drain extensions that protrude into the channel region before gate formation. The process sequence is: (1) deposit sacrificial material and form patterned structures, (2) perform dopant activation annealing, (3) open regions by removing sacrificial material, (4) deposit nanocrystal charge trapping units, (5) form gates that extend over the channel region. The source/drain extensions are formed to protrude into the channel region by a controlled amount (e.g., 5-20 nm) to eliminate gaps between the extensions and gates, ensuring direct electrical contact and minimizing on-resistance while maintaining fabrication simplicity through the patterned sacrificial material approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the effective integration of nanocrystals with improved charge retention and density, enhancing the performance of nonvolatile memory cells by eliminating gaps between source/drain extensions and gates, thus reducing on-resistance and improving memory cell performance.
Implementation Method 1
the effects of Coulomb blockade, quantum confinement, and reduction of charge leakage from weak spots in tunnel oxide
Implementation Method 2
the effects of Coulomb blockade, quantum confinement, and reduction of charge leakage from weak spots in tunnel oxide
Implementation Method 3
A new method has been developed for deposition of nanocrystals which utilizes chaperonin protein to form a template for retaining nanocrystals in desired orientations
Data Source
AI summary
Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.