Fin-Type Semiconductor Device With Nano-Sheet Gate Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Down-scaled semiconductor devices face challenges in reducing parasitic capacitance, which hinders performance enhancement due to the limitations of existing device structures and manufacturing methods.
Innovation Solution
The semiconductor device incorporates a fin-type active region with nano-sheets and a gate structure that includes a main gate portion and sub-gate portions, along with an inner spacer and source/drain protection layer, to minimize parasitic capacitance between the gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If down-scaling of semiconductor device is performed to reduce size, then device size is reduced, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode, second gate electrode, third gate electrode) positioned at different heights and locations. This segmentation allows each gate segment to control specific channel regions independently, reducing overlap capacitance between gate and source/drain while maintaining effective channel control in the down-scaled device
Solution Approach 2:
The patent introduces vertical dimensionality by forming gate electrodes at different heights (using different fill levels in trenches) and creating a three-dimensional gate structure. The first gate electrode is at a lower level, while second and third gate electrodes are at higher levels, enabling control of channel regions from multiple vertical perspectives and reducing parasitic capacitance through spatial separation
2Ease of manufacture
If conventional device structure is used, then manufacturing is simpler, but parasitic capacitance cannot be reduced effectively
Solution Approach 1:
The patent performs preliminary actions by forming isolation regions and positioning sacrificial layers before forming the gate electrodes. The sacrificial layers are pre-positioned to define future gate locations, and isolation regions are formed to prevent unwanted electrical connections. This preliminary structuring enables the complex multi-level gate configuration to be manufactured systematically
Solution Approach 2:
Sacrificial layers are used as intermediary structures during manufacturing. These layers are temporarily formed to define gate electrode positions and are subsequently removed after gate formation. The sacrificial layers mediate the manufacturing process by providing a template for gate placement without being part of the final functional device, simplifying the overall manufacturing approach
Data Source
AI summary
A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.