Self-aligned split gate memory using spacer and in-laid formation
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Solution Overview
Problem
In the manufacture of semiconductor non-volatile memory devices, existing lithography techniques face challenges with gate misalignment control and scalability, and the removal of parasitic control and select gate structures adds complexity and requires additional process steps.
Innovation Solution
A method of forming self-aligned in-laid split gates using a combination of spacer and in-laid formation, which relaxes stringent alignment requirements and avoids the need for parasitic dummy gate structures, allowing for scalable integration without additional photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography techniques are used for gate formation, then gate alignment can be achieved, but stringent alignment tolerances and scaling limitations occur
Solution Approach 1:
The gate structure is divided into two separate gates formed in distinct openings through the nitride layer, allowing independent formation and alignment of each gate without requiring tight mutual alignment tolerances
Solution Approach 2:
A nitride layer is introduced as an intermediary sacrificial structure that defines the openings for both gates, serving as a template that relaxes alignment requirements by allowing each gate to be independently positioned relative to the nitride openings rather than requiring precise gate-to-gate alignment
2Reliability
If parasitic dummy control gate and select gate structures are formed and then removed, then actual gates can be protected during processing, but process complexity and additional photolithography steps are required
Solution Approach 1:
The protective function previously performed by parasitic dummy gate structures is eliminated entirely by using the nitride layer openings and spacer formation to inherently define and protect the gate regions during processing
Solution Approach 2:
The gate structures self-align and self-protect through the spacer formation process, where spacers automatically form on the sides of the deposited material, providing inherent protection without requiring additional dummy structures or protective layers
3Adaptability or versatility
If spacer and in-laid formation are used for split gate definition, then alignment requirements are relaxed and scalability is improved, but process steps must be carefully sequenced
Solution Approach 1:
The nitride layer is formed and patterned with openings before any gate material deposition, establishing the geometric template in advance that guides subsequent spacer formation and gate material deposition, ensuring proper alignment without tight tolerances
Solution Approach 2:
The formation of control gates and select gates is merged into a single continuous process flow using the same nitride layer template and spacer formation technique for both gate types, improving scalability while maintaining clear process sequencing
Data Source
AI summary
A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.