Dual Chip Clock Synchronization via Slow-Speed Counter Calibration
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Solution Overview
Problem
Conventional logic devices face challenges in synchronizing semiconductor circuits operating at different speeds, leading to data loss and reduced efficiency due to skew issues, as they often lack the ability to calibrate counters effectively when components operate at varying frequencies.
Innovation Solution
The method involves setting semiconductor circuits to a common clock source at a slow speed, synchronizing division counters, and then switching to a faster speed while maintaining synchronization through pulse alignment and deskewing techniques, using programmable delay lines and skew sensors to minimize skew and ensure proper data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor circuits operate at high clock speeds, then processing speed and productivity are improved, but synchronization accuracy and data reliability deteriorate due to skew issues between circuits
Solution Approach 1:
The patent applies preliminary action by performing counter calibration at a slow clock speed before switching to fast clock speed. The division counters are synchronized and calibrated while operating at slow speed where the IO can reliably process data, ensuring proper alignment is established in advance before high-speed operation begins.
Solution Approach 2:
The patent implements dynamics by using programmable delay lines that can dynamically adjust skew compensation. The delay lines are configured based on calibration results obtained at slow clock speed, and this configuration is maintained during fast clock speed operation to dynamically compensate for skew issues that would otherwise occur at higher speeds.
2Measurement precision
If division counters are synchronized at slow clock speed, then synchronization accuracy is improved, but processing speed deteriorates during the calibration phase
Solution Approach 1:
The patent applies periodic action by alternating between slow clock speed calibration phases and fast clock speed processing phases. During calibration, the system operates at slow speed to achieve precise counter synchronization, then switches to fast speed for normal processing, creating a periodic pattern of calibration and operation.
Solution Approach 2:
The calibration at slow clock speed is performed as a preliminary action before normal high-speed processing. This ensures that the division counters are properly synchronized in advance, so that when the system switches to fast clock speed, the synchronization is already established and no additional calibration is needed during high-speed operation.
3Reliability
If the IO operates at slow clock speed during calibration, then data reliability is improved, but the system cannot utilize fast clock speed capabilities during calibration
Solution Approach 1:
The slow-speed calibration phase is performed as a preliminary action to establish proper synchronization between division counters. Once calibration is complete and synchronization is verified, the system transitions to fast clock speed operation, ensuring that the IO only operates at slow speed during the necessary calibration period, not during normal processing.
Solution Approach 2:
The system dynamically adjusts clock speed based on operational requirements. The IO operates at slow clock speed only during calibration when data reliability is critical, then the system switches to fast clock speed for normal processing where the previously established synchronization ensures continued reliability at higher speeds.
Data Source
AI summary
Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.