Dual-Clock AD Conversion for Low-Power Image Sensor Readout
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Solution Overview
Problem
Existing AD conversion methods, such as those described in Patent Documents 1, 2, and 3, require complex circuit configurations and high power consumption, with limited accuracy and increased complexity due to separate processing of higher and lower order bits using different reference signals, leading to inefficiencies in power reduction and bit accuracy.
Innovation Solution
A data processing apparatus utilizing a reference signal comparison type AD conversion method with a counter section operating on two distinct clocks, a high-speed clock for lower order bits and a low-speed clock for higher order bits, allowing independent control and power reduction by selectively stopping one counter section during operation of the other, while maintaining bit accuracy through compensation between the two counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate processing of higher and lower order bits using different reference signals is implemented, then power consumption is reduced, but circuit complexity increases and bit accuracy deteriorates
Solution Approach 1:
The patent divides the counter into two independent sections: a higher order bit counter and a lower order bit counter. Each counter operates independently with its own clock signal, allowing separate control and processing. This segmentation enables the higher order bit counter to operate at lower speed while the lower order bit counter handles higher speed operations, reducing overall power consumption while maintaining simplicity through modular design.
Solution Approach 2:
The patent changes the operating parameters of different counter sections by assigning different clock frequencies: a first clock for the higher order bit counter and a second clock for the lower order bit counter. This parameter differentiation allows each counter to operate optimally for its bit range, reducing power consumption in the higher order section while maintaining accuracy through compensation mechanisms.
2Use of energy by moving object
If separate processing of higher and lower order bits using different reference signals is implemented, then power consumption is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the lower order bit counter compensates for excess or deficiency in the higher order bit counter's count values. The compensation amount is calculated based on the difference between the actual count and the expected count, and this compensation is applied to correct the higher order bit results. This feedback loop ensures measurement precision is maintained even though the higher order counter operates independently with potentially lower accuracy.
Solution Approach 2:
The patent employs asymmetric processing where the lower order bit counter operates with higher precision and speed to compensate for the higher order bit counter's limitations. The compensation mechanism treats the two counter sections differently, with the lower order section serving as the reference for correcting the higher order section's measurements, thus maintaining overall bit accuracy.
3Use of energy by moving object
If counter sections operate independently with different clocks, then power consumption is reduced by selective stopping, but device complexity increases
Solution Approach 1:
The patent makes the counter operation dynamic by enabling independent control of each counter section's clock signals. The higher order bit counter can be stopped or operated at reduced speed when not needed, while the lower order bit counter continues operating at full speed. This dynamic control allows the system to adapt power consumption to actual processing needs, reducing energy waste during operations that don't require full counter functionality.
Data Source
AI summary
Disclosed herein is a data processing method wherein an analog processing object signal is compared with a reference signal and used to convert the processing object signal into digital data and a counting process is carried out and then a count value at a point of time at which the counting process is completed is retailed to acquire digital data of N bits of the processing object signal, including the steps of: carrying out counting operations using the first and second count clocks, whose frequencies are different by an amount corresponding to a weight of the bits from each other, independently of each other; and compensating for an excess or deficiency of data of the higher order N-M bits counted using the second count clock with respect to the count value counted using the first count clock within the counting operation enabled period.