Dual-Clock Timestamping for Low-Power Fine Time Resolution
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Solution Overview
Problem
Low power communications devices face challenges in generating and measuring accurate time intervals with high precision while minimizing power consumption, as existing high precision clock sources require continuous operation and increased power usage, especially when needing multiple frequency sources or higher timestamp resolution.
Innovation Solution
A clock generation system using a lower frequency clock source coupled with a programmable counter to power a higher frequency clock source only when necessary, combined with a timestamp generator that utilizes a high speed clock powered by external events for fine-grain timestamping and frequency correction of unstable oscillators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high precision clock source is used continuously, then time interval accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling the high frequency clock source only during specific intervals when high precision timing is needed, rather than running it continuously. The system switches between low frequency clock for normal operation and high frequency clock for precision measurements, thereby reducing overall power consumption while maintaining time interval accuracy when required.
Solution Approach 2:
The system dynamically adjusts the clock frequency based on operational requirements. It transitions from a static continuous high frequency operation to a dynamic system that selects between low and high frequency modes, optimizing the balance between power consumption and timing precision according to real-time needs.
2Adaptability or versatility
If multiple frequency sources are used, then frequency flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple frequency sources (low frequency and high frequency clock sources) into a unified timing system with a single control mechanism. Instead of maintaining completely separate frequency generation systems, the invention integrates them under one control logic that selectively enables the appropriate frequency source, thereby achieving frequency flexibility while limiting the increase in system complexity.
Data Source
AI summary
A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.