Dual-Clock Timing for Fine Resolution in Low-Power Systems
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Solution Overview
Problem
Low power communications devices face challenges in generating and measuring accurate time intervals with high precision while minimizing power consumption, as existing high precision clock sources require continuous operation and increased power usage, especially when needing multiple frequency sources or high-resolution timestamp generation.
Innovation Solution
A clock generator system using a lower frequency clock source coupled with a programmable counter to power a higher frequency clock source only when necessary, allowing for fine-grained control and power efficiency, along with a timestamp generator that utilizes a high-speed clock powered by external events for precise timestamping and frequency correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high precision clock source is used continuously, then time interval accuracy is improved, but power consumption increases
Solution Approach 1:
The high frequency clock source is activated periodically only when high precision time measurement is required, rather than running continuously. The system switches between low frequency clock for normal operation and high frequency clock for precision measurements, achieving both accuracy and power efficiency.
Solution Approach 2:
The clock frequency is dynamically adjusted based on the operational requirements. The system can switch between different clock sources (low frequency and high frequency) depending on whether precision timing is needed, optimizing the balance between accuracy and power consumption.
2Adaptability or versatility
If multiple frequency sources are used, then frequency flexibility is improved, but device complexity increases
Solution Approach 1:
The system combines a low frequency clock source and a high frequency clock source into a unified clock management architecture. Both clock sources share common control logic and counters, allowing the system to achieve multiple frequency capabilities while minimizing the increase in overall system complexity.
Solution Approach 2:
The clock management system is designed to serve multiple functions: it can operate in low power mode using the low frequency clock, switch to high precision mode using the high frequency clock, and provide intermediate frequencies through programmable dividers. This multi-functionality reduces the need for separate dedicated circuits for each function.
3Measurement precision
If a higher frequency clock is used for timestamp generation, then timestamp resolution is improved, but steady state current increases
Solution Approach 1:
The high frequency clock used for timestamp generation is activated only periodically when external events require timestamping, rather than running continuously. This periodic activation maintains high timestamp resolution capability while significantly reducing the average steady state current consumption.
Solution Approach 2:
The high frequency clock function is extracted from the continuous operation domain and applied only when specifically needed for timestamp generation. This separates the high precision timing function from the continuous clocking requirement, allowing the system to use lower power clocking for normal operations.
Data Source
AI summary
A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.