Dual-Core Clock Fractional Divider for Error Detection
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Solution Overview
Problem
Existing clock fractional divider modules in integrated circuit design are inadequate in detecting and correcting errors, leading to potential system failures, particularly in systems where clock generation and control are critical.
Innovation Solution
A dual-core lock step unit is integrated into the clock fractional divider module, comprising a master clock fractional divider module core unit and a checker clock fractional divider module core unit, along with a lock-step comparing unit, to enhance error detection and correction capabilities through direct-digital-synthesizer functionality and XOR logic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock fractional divider module is used, then the hardware design complexity is limited and power consumption is controlled, but error detection and correction capabilities are insufficient leading to potential system failures
Solution Approach 1:
The clock fractional divider is divided into two independent cores: a master core that performs the actual clock division and a checker core that performs error detection. This segmentation allows the system to detect errors without significantly increasing the complexity of the main functional unit, as the checker core operates independently with the same input signals.
Solution Approach 2:
The checker core is designed as a copy of the master core's logic structure, receiving the same input signals (reference clock, numerator, denominator) and performing identical computational operations. This copying approach enables error detection through comparison without requiring complex error detection logic, thereby limiting the increase in hardware complexity.
2Reliability
If error detection and correction mechanisms are added to the clock fractional divider, then system reliability improves, but hardware design complexity increases
Solution Approach 1:
The system implements feedback by continuously comparing the output clock signals from the master core and checker core. When a discrepancy is detected, the comparison result feeds back to indicate an error condition, enabling the system to detect and correct errors without complex intervention logic.
Solution Approach 2:
A comparison mechanism acts as an intermediary between the master core and checker core outputs. This intermediary component simplifies the error detection process by directly comparing the two clock signals and generating an error indicator, avoiding the need for complex analysis logic in either core.
3Reliability
If dual-core lock step architecture is implemented, then common-cause fault detection improves, but power consumption increases
Solution Approach 1:
The dual-core architecture operates in lock-step periodic cycles, where both cores process the same input signals simultaneously and their outputs are compared at regular intervals. This periodic operation allows error detection while maintaining controlled power consumption, as the additional checker core only needs to operate synchronously with the master core rather than continuously at full power.
Data Source
AI summary
A clock fractional divider module which is formed as, comprises or has integrated therein a dual-core lock step unit. The dual-core lock step unit is configured in order to realize a clock fractional division arrangement, mechanism or process accompanied by an error detection, recognition and/or correction arrangement, mechanism or process.