Fault Response TRIZ Cases
- Inline Trace Compression Using Differential Frames and Bit Flags
Differential frame encoding with zero, one-hot, and two-hot bit flags cuts emulation trace storage and DDR bandwidth demand.
- Polar Code Sequence Construction for Flexible Puncturing Rates
Prebuilt reliability-sorted channel indexes let polar codes adapt to different puncturing or shortening rates with lower storage overhead and bit error.
- Dual-Core Clock Fractional Divider for Error Detection
A lock-step master and checker divider compares clock signals to detect and correct faults in fractional clock generation.
- Hardware Secure Element Message Handling for Low-Latency Encryption
Dedicated hardware message and error handling cuts latency and power use in secure element encryption communication.
- PCIe Error Reporting via Hybrid Hardware-Software Mediation
Hardware detects PCIe packet errors while software assigns attributes and function ownership, enabling scalable reporting without hardware re-spin.
- Error-Corrected Data Stream Steganography Against Traffic Analysis
Confidential bits are hidden as correctable bit faults in a normal data stream, avoiding size and traffic cues that expose separate encrypted messages.
- Watchdog Timer Self-Diagnosis During Semiconductor Operation
A suppressing and holding circuit lets a watchdog timer diagnose reset faults during operation without disrupting normal semiconductor use.
- Polar Code Rate Matching with Reliability-Sorted Channel Indexes
Uses puncturing or shortening proportions with prestored reliability-sorted channel indexes to cut polar code storage overhead and bit errors.
- Watchdog Timer Fault Diagnosis During Semiconductor Operation
A suppressing and holding circuit lets a watchdog timer diagnose faults during refresh periods without disrupting program execution.
- Spare Memory Rotation for Low-Movement DSN Rebuilds
When a DS memory fails, remapping slices to a spare and rebuilding only the affected range cuts data movement while preserving DSN reliability.
- PCIe Error Reporting with Hybrid Hardware-Software Management
Hardware detects PCIe transaction errors while software assigns attributes and owners, avoiding costly hardware re-spin for reporting updates.
- Non-Intrusive IC Monitoring With Incremental Debug Reconfiguration
Incremental configuration enables real-time IC debug and event response without recompilation, downtime, or disruption to the user design.