Watchdog Timer Fault Diagnosis During Semiconductor Operation

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Solution Overview

Problem

Existing semiconductor devices with watchdog timers cannot perform fault diagnosis during actual operation, which poses safety concerns, especially in vehicle applications where functional safety is critical.

Innovation Solution

Incorporating a watchdog timer with a counter, counter control circuit, and fault diagnosis module that includes a suppressing circuit to prevent reset signal generation during refresh periods and a holding circuit to detect and hold reset signals, allowing for fault diagnosis during normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fault diagnosis is performed during actual operation, then functional safety is improved, but the risk of interfering with program execution increases

Engineering Contradiction:
Improvefunctional safetyVSAvoidinterference with program execution
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The fault diagnosis function is activated periodically during refresh periods rather than continuously. The counter control circuit sets the counter to a specific value during refresh periods, creating periodic intervals for fault diagnosis that do not continuously interfere with program execution. This periodic activation allows safety monitoring while minimizing disruption to normal operations.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The suppressing circuit acts as an intermediary between the counter overflow detection and the reset signal output. When the counter overflows during refresh periods, the suppressing circuit prevents the reset signal from being output to the external system, while still allowing internal fault diagnosis to occur. This intermediary mechanism isolates the fault diagnosis process from the main program execution path.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a watchdog timer is used to monitor program execution, then system reliability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fault diagnosis function is merged with the existing watchdog timer circuit by utilizing the same counter and control structures. The counter control circuit performs both normal watchdog timing functions and fault diagnosis functions by setting the counter to specific values during refresh periods. This merging approach enables enhanced reliability without proportionally increasing circuit complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The counter control circuit is designed with multi-functionality, serving both as a watchdog timer and a fault diagnosis mechanism. The same counter structure is used for monitoring program execution and for detecting faults during refresh periods. This universal design reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while maintaining improved system reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the counter is set to a specific value during refresh periods, then fault diagnosis capability is improved, but the time for normal timing operations is reduced

Engineering Contradiction:
Improvefault diagnosis capabilityVSAvoidtiming operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The counter is set to a specific value periodically during refresh periods rather than continuously. These refresh periods are brief intervals within the overall watchdog timer operation cycle. By confining the counter setting action to periodic refresh intervals rather than continuous operation, the fault diagnosis capability is enhanced while the loss of time for normal timing operations is minimized to only these brief periodic intervals.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The counter is set to a specific value only partially during refresh periods rather than throughout the entire watchdog timer operation. This partial action is sufficient to enable fault diagnosis during these intervals without excessively reducing the time available for normal timing operations. The refresh periods are designed to be brief, ensuring that the partial action does not significantly impact overall timing performance.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3343373B1Semiconductor device comprising watchdog timer
Publication Date: 2019.11.13 RENESAS ELECTRONICS CORP
  • EP3343373B1 patent drawingFigure 1
  • EP3343373B1 patent drawingFigure 2
  • EP3343373B1 patent drawingFigure 3

AI summary

The aim of the present disclosure is to provide a watchdog timer that can perform a fault diagnosis during the actual use of a semiconductor device. In a semiconductor device provided with a watchdog timer, the watchdog timer includes a counter; a counter control circuit that changes a count value of the counter to a desired value in the refresh period of the count value; and a fault diagnosis module. The fault diagnosis module includes a suppressing circuit that suppresses generation of a reset signal to the exterior of the watchdog timer in the refresh period; and a holding circuit that holds the reset signal.