Hardware Secure Element Message Handling for Low-Latency Encryption
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Solution Overview
Problem
Existing secure processing systems in automotive applications face challenges in efficient communication between non-secure and secure processing units, particularly in handling encryption and decryption operations, which can lead to latency and robustness issues due to complex software-based message handling and error handling processes.
Innovation Solution
A hardware secure element with a message handler module and parameter check module is introduced, utilizing a look-up table to determine software routines for encryption and decryption operations, and performing error handling in hardware to minimize latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based message handling and error handling processes are used in secure processing systems, then the system can handle encryption and decryption operations, but latency and robustness issues occur due to complex processing
Solution Approach 1:
The patent replaces software-based message handling and error handling with dedicated hardware modules. The message handler module is implemented as hardware logic that directly processes messages between secure and non-secure processing units, eliminating software interpretation overhead. Similarly, error handling is performed by hardware circuits that detect and respond to errors immediately, rather than through software exception handling, thereby reducing latency while maintaining robustness.
Solution Approach 2:
The patent introduces a dedicated message handler module as an intermediary component between secure and non-secure processing units. This hardware intermediary efficiently manages communication protocols, message routing, and error handling, reducing the complexity and latency associated with software-based mediation while improving system robustness.
2Productivity
If dedicated hardware implementation of message handling and error processing is used, then latency and power consumption are reduced, but device complexity increases
Solution Approach 1:
The patent segments the secure processing system into distinct functional modules: a message handler module for communication management, an error handler module for error processing, and encryption/decryption modules. Each module is implemented as dedicated hardware with specific responsibilities, which improves efficiency through parallel processing while managing complexity through modular design and clear separation of concerns.
Solution Approach 2:
The message handler module is designed as a universal hardware component that can manage multiple types of communication protocols and message formats between secure and non-secure processing units. This multi-functional design improves efficiency by handling diverse communication tasks within a single hardware module, reducing overall system complexity compared to having separate dedicated circuits for each communication type.
Data Source
AI summary
A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.