Dual-Damascene Process for Thick Copper Wire Fabrication
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Solution Overview
Problem
The dual-damascene process for fabricating super thick copper wires faces challenges such as void formation and corrosion due to difficulties in the second lithography step, leading to incomplete via fill and preferential etching issues during the reactive ion etching process.
Innovation Solution
A method involving selective etching in a dual-damascene process, where a border is formed around partial vias using negative photoresist and etch stop layers, allowing for thick wiring while preventing etching through to the underlying metal or MIM capacitor, thereby eliminating voids and corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography with ARC is used for via formation in dual-damascene process, then via fill can be achieved, but large voids form in the via and corrosion occurs in underlying metal layer
Solution Approach 1:
The patent segments the via formation process into two distinct steps: first forming a partial via to a first depth, then forming the remaining via to a second depth. This segmentation allows each etching step to be optimized independently, preventing void formation while maintaining complete via fill. The border formation around the partial via further segments the etching zones, enabling precise control over etch depth and preventing corrosion of underlying layers.
Solution Approach 2:
The patent performs preliminary actions by forming the partial via and border structure before completing the via etch. The border is formed around the partial via using negative photoresist, creating a defined boundary that prevents etchant from causing corrosion in underlying metal layers. This preliminary structuring ensures that when the remaining via is etched, voids are prevented while maintaining reliability.
2Manufacturing precision
If thicker ARC is used to improve via fill, then better fill properties are achieved, but resist erosion and massive fencing occur during trough RIE
Solution Approach 1:
The patent applies partial action by forming only a partial via to a first depth in the first etching step, rather than etching the complete via depth. This partial etching, combined with border formation, achieves adequate via fill preparation without requiring excessively thick ARC. The remaining via is then completed in a second etching step, avoiding the resist erosion and fencing problems associated with thick ARC during trough RIE.
3Ease of manufacture
If single damascene process is used for super thick copper wire fabrication, then integration problems are avoided, but the process cannot achieve the required wire thickness and reliability
Solution Approach 1:
The patent segments the dual-damascene process into controlled etching steps with border formation, where a partial via is etched to a first depth, a border is formed, then the remaining via is etched to a second depth. This segmentation enables precise control over via dimensions and fill quality, achieving the required manufacturing precision for super thick copper wires while maintaining practical process integration through systematic process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures complete via fill without voids, prevents corrosion, and maintains the integrity of the underlying metal and MIM capacitor, enabling the fabrication of thick copper wires with improved reliability and reduced etching complications.
Implementation Method 1
The forming of the border comprises forming a negative photoresist on the stacked structure and exposing portions of the negative photoresist remote from the at least one partial via
Implementation Method 2
due to large fences or rails generated around the vias during trough RIE. More specifically, during the RIE process using the thicker ARC fill
Data Source
AI summary
A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.