Multi-Phase Clock Generator Using Dual Delay Lines for Duty-Cycle Accuracy
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Solution Overview
Problem
Existing multi-phase clock signal generators produce clock signals with duty-cycle distortion, which is problematic in high-speed electronic systems requiring accurate phase relationships and duty-cycle correction over a wide frequency range, especially in environments with power supply noise and clock jitter.
Innovation Solution
A multi-phase duty-cycle corrected clock signal generator using a multi-tap adjustable delay line, phase detector, charge-pump and loop filter, and bias generator to synchronize clock signals and correct duty-cycle distortion, ensuring accurate phase relationships and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-tap adjustable delay line is used to generate multi-phase clock signals, then phase relationships can be established, but duty-cycle distortion occurs
Solution Approach 1:
The clock signal generation is divided into multiple independent phases using a multi-tap delay line, where each tap generates a separate phase. This segmentation allows precise phase control while the duty-cycle correction circuit independently corrects each phase to eliminate distortion.
Solution Approach 2:
A duty-cycle correction circuit is implemented that uses feedback to detect and correct duty-cycle distortion in the generated clock phases. The circuit monitors the duty-cycle of each phase and adjusts timing to compensate for deviations, ensuring accurate 50% duty-cycles despite the phase-shifting operations.
2Device complexity
If a fixed timing circuit is used to generate quadrature clock signals, then simple circuit implementation is achieved, but adaptability to wide frequency ranges is lost
Solution Approach 1:
The delay line is designed with adjustable delay elements that can be dynamically configured to adapt to different clock frequencies. This dynamic adjustment capability allows the circuit to maintain accurate phase relationships across a wide frequency range while keeping the overall circuit structure relatively simple.
Solution Approach 2:
The multi-tap delay line structure serves multiple functions: it generates multiple phase shifts simultaneously, provides frequency adaptability through adjustable delays, and enables duty-cycle correction. This multi-functional design eliminates the need for separate circuits for each function, maintaining simplicity while achieving versatility.
3Measurement precision
If duty-cycle correction is implemented in high-speed systems, then accurate clock signals are achieved, but power consumption increases
Solution Approach 1:
The duty-cycle correction circuit is designed to operate autonomously using the existing clock phases and delay line infrastructure. It self-adjusts the duty-cycles by utilizing the same delay elements and timing mechanisms already present in the phase generation circuit, eliminating the need for additional high-power correction circuits.
Data Source
AI summary
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.