Dual Delay-Locked Pulse Circuit for Stable ToF Timing

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Solution Overview

Problem

Existing pulse generation circuits in Time of Flight (ToF) systems face challenges in accurately generating delayed pulses with consistent delay times, especially when the clock signal frequency varies, leading to fluctuations in delay amounts and pulse widths, which affect ranging accuracy and can cause radio disturbances.

Innovation Solution

The proposed pulse generation circuit includes a first delay-locked loop circuit and a second delay-locked loop circuit connected in series, allowing for precise control of delay amounts by adjusting current ratios in charge pumps, ensuring consistent delay times even with frequency variations in the clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional pulse generation circuit is used, then the circuit structure is simple, but the delay time becomes unstable when clock frequency varies

Engineering Contradiction:
Improvedelay time stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic delay adjustment by introducing a delay amount adjustment unit that modifies the delay time of the delay circuit based on detected clock frequency variations. This dynamic adaptation ensures stable delay output despite frequency changes, resolving the contradiction between simple structure and stable performance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the output signal is fed back to detect clock frequency, and this frequency information is used to adjust the delay amount in real-time. The feedback loop compensates for frequency variations, maintaining delay stability without requiring a completely complex circuit redesign.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If delay time is increased to improve ranging accuracy, then ranging precision improves, but pulse width becomes inconsistent

Engineering Contradiction:
Improveranging accuracyVSAvoidpulse width consistency
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The patent changes the delay time parameter independently of the pulse width parameter by using a dedicated delay circuit with adjustable delay amount. This allows precise control of delay time for improved ranging accuracy while maintaining consistent pulse width through separate control mechanisms.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If clock frequency is increased to improve productivity, then signal processing speed improves, but delay time becomes unstable

Engineering Contradiction:
Improvesignal processing speedVSAvoiddelay time stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent makes the delay circuit dynamic by continuously adjusting its delay amount based on real-time clock frequency detection. This allows the system to operate at high clock frequencies for improved productivity while maintaining stable delay times through active compensation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies preliminary anti-action by pre-adjusting the delay amount in response to detected frequency changes before they affect the delay output. The frequency detection and adjustment mechanism proactively compensates for upcoming frequency variations, preventing delay instability.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS12603653B2Pulse generation circuit
Publication Date: 2026.04.14 ASAHI KASEI MICRODEVICES CORP
  • US12603653B2 patent drawing
  • US12603653B2 patent drawing
  • US12603653B2 patent drawing

AI summary

Provided is a pulse generation circuit that receives a clock signal and outputs a delayed pulse signal, including: a first delay-locked loop circuit that receives the clock signal and generates a first delay signal obtained by delaying the clock signal; a second delay-locked loop circuit that generates a second delay signal with reference to the first delay signal; and an output circuit that outputs the delayed pulse signal according to the first delay signal and the second delay signal. The second delay-locked loop circuit may have: a second charge pump that outputs a current according to the clock signal and the delayed pulse signal; and a second delay circuit that outputs the second delay signal obtained by delaying the clock signal according to a current output by the second charge pump.