Dual-Die Semiconductor Package With Interposing Substrate
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Solution Overview
Problem
In 3D semiconductor packaging, signal transmission delays occur due to longer signal paths between upper semiconductor dies and I/Os, limiting integration density and performance.
Innovation Solution
A dual-die semiconductor package design featuring a bottom device die bonded to a package substrate, an interposing package substrate located between the bottom and top device dies, and additional power and ground planes provided by the interposing substrate to reduce signal loss and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked in 3D packaging to increase integration density, then the volume utilization and component density are improved, but the signal transmission path length increases causing signal delays
Solution Approach 1:
The patent transitions from traditional 2D packaging to 3D stacked packaging, utilizing the vertical z-direction to increase integration density. Multiple semiconductor dies are stacked vertically on the package substrate, allowing more components to be integrated within the same footprint area, thus resolving the contradiction by moving from planar to spatial integration.
Solution Approach 2:
The patent introduces an interposing substrate positioned between the lower and upper semiconductor dies. This intermediary structure provides additional power and ground planes that reduce signal loss and transmission delays by providing shorter signal paths and better power delivery to the upper die, thus mitigating the signal delay issue while maintaining 3D stacking benefits.
2Speed
If the signal path length is reduced to improve transmission speed, then signal delay is decreased, but the ability to stack multiple dies vertically is limited
Solution Approach 1:
The interposing substrate acts as a mediator between the lower and upper dies, providing additional power and ground planes that reduce signal path length and improve transmission speed. This intermediary structure enables better electrical connectivity without preventing vertical stacking, thus improving speed while managing the complexity through a modular design.
Solution Approach 2:
The package structure is segmented into multiple functional layers: package substrate, lower die, interposing substrate, and upper die. This segmentation allows each layer to be optimized independently, with the interposing substrate specifically designed to provide power/ground planes for signal integrity, thus managing complexity through functional decomposition.
3Reliability
If additional power and ground planes are added to reduce signal loss, then signal quality is improved, but the package structure becomes more complex
Solution Approach 1:
The interposing substrate serves as a dedicated intermediary layer that provides additional power and ground planes specifically for improving signal quality to the upper die. By concentrating the power/ground plane function in this intermediate layer, the design improves signal reliability without requiring complete redesign of the entire package structure.
Solution Approach 2:
The interposing substrate provides localized power and ground planes specifically where needed - between the lower and upper dies. This local quality enhancement targets the specific area requiring improved signal quality, rather than uniformly increasing complexity throughout the entire package structure.
Data Source
AI summary
The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.