Dual Dielectric Forksheet Pillar for nFET-pFET Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving precise physical and electrical isolation between nFET and pFET channel nanosheets, limiting the miniaturization and performance of forksheet transistors.
Innovation Solution
The introduction of a dual dielectric pillar, comprising a first dielectric and a second dielectric different from the first, is used to physically and electrically separate the nFET and pFET channel nanosheets, allowing for tighter spacing and improved transistor performance by forming a trench within the dielectric pillar and depositing the second dielectric material within it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single dielectric pillar is used to separate nFET and pFET channel nanosheets, then physical isolation is achieved, but electrical isolation is insufficient limiting miniaturization
Solution Approach 1:
The single dielectric pillar is segmented into a dual dielectric pillar structure with first and second dielectric materials positioned at different heights. This segmentation allows each dielectric material to perform specialized isolation functions, achieving both physical and electrical isolation between nFET and pFET channel nanosheets, thereby resolving the contradiction between isolation precision and device structure complexity.
Solution Approach 2:
Different dielectric materials are used at different locations (heights) within the pillar structure. The first dielectric material is positioned to provide isolation at one level while the second dielectric material provides isolation at another level. This local differentiation of material properties enables precise control of electrical isolation characteristics without requiring complete structural redesign.
2Productivity
If tighter spacing between nFET and pFET is implemented, then device miniaturization is achieved, but isolation between channels deteriorates
Solution Approach 1:
The isolation structure transitions from a single-level dielectric pillar to a dual-level dielectric pillar structure. By adding the vertical dimension with two different dielectric materials at different heights, the patent achieves enhanced isolation effectiveness without increasing lateral spacing requirements, thus enabling tighter device spacing while maintaining reliable channel isolation.
Solution Approach 2:
The dielectric pillar is constructed as a composite structure with two different dielectric materials. This composite approach leverages the complementary properties of each dielectric material to provide superior isolation performance compared to a single dielectric material, allowing tighter spacing while maintaining reliability.
Data Source
AI summary
A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.