Dual-Domain Dynamic Multiplexer for Asynchronous Voltage Domain Transition
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Solution Overview
Problem
Asynchronous FIFO memory implementations face challenges in transitioning between varying write and read voltage domains, leading to metastability issues and difficulties in meeting setup and hold constraints, due to large variations in insertion delay.
Innovation Solution
A dynamic multiplexer is used to transition between voltage and frequency domains, powered by a read voltage source and clocked by a read clock, allowing data to be latched and multiplexed from the write domain to the read domain, while maintaining the FIFO memory in the write domain, with level shifters facilitating voltage transitions and programmable clock delays aligning clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous FIFO memory is used to buffer data between devices operating at different clock speeds, then flow control and buffering functions are achieved, but metastability issues arise leading to data errors
Solution Approach 1:
The patent applies preliminary action by pre-charging the readline to the read voltage level before data transfer occurs. This pre-charge operation ensures that the readline is ready to accept data from the asynchronous data line, reducing metastability risks by establishing a known initial state before the actual data transition happens
Solution Approach 2:
The patent uses an intermediary mechanism (the pre-charge stage and controlled coupling circuitry) to mediate the data transfer between the asynchronous write domain and read domain. This intermediary structure allows gradual voltage domain transition and provides controlled interaction between the two asynchronous domains, reducing direct metastability conflicts
2Adaptability or versatility
If level shifters are used to transition between voltage domains, then voltage transitions are facilitated, but insertion delay variations increase making it difficult to meet setup and hold constraints
Solution Approach 1:
The patent applies dynamics by making the multiplexer powering and clocking adaptive rather than fixed. The multiplexer can be powered by either the write voltage or read voltage depending on the operational phase, and clocked by either write clock or read clock. This dynamic reconfiguration optimizes timing performance for each specific operation, reducing insertion delay variations and enabling better compliance with setup and hold constraints
Solution Approach 2:
The patent changes operating parameters (voltage level and clock source) of the multiplexer dynamically based on the operational phase. During write operations, the multiplexer operates in write domain parameters; during read operations, it switches to read domain parameters. This parameter changing approach allows the system to adapt to different timing requirements and reduces delay variations
Data Source
AI summary
A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.