Dual ECC Layout for Memory Arrays Balancing Density and Read Speed
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Solution Overview
Problem
Memory devices face challenges in efficiently performing error correction operations due to the space occupied by Error Correction Code (ECC) circuits, which can reduce memory cell density and operational efficiency.
Innovation Solution
The implementation of a dual ECC circuit configuration, where a first ECC circuit is located under the memory cell array to maintain density and perform write operations efficiently, and a second ECC circuit, positioned outside, focuses on faster read operations, allowing for independent optimization of write and read error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single ECC circuit is used for both write and read operations, then device complexity is reduced, but operational efficiency and speed for different operations cannot be independently optimized
Solution Approach 1:
The ECC circuit is segmented into two separate circuits: a first ECC circuit coupled with the memory cell array for write operations, and a second ECC circuit for read operations. This segmentation allows each circuit to be independently optimized for its specific operation type, improving overall operational efficiency while maintaining manageable device complexity through functional separation.
2Reliability
If ECC circuits are placed outside the memory cell array, then error correction operations can be optimized, but memory cell density is reduced
Solution Approach 1:
Different regions of the memory device are assigned different functions with different quality requirements. The first ECC circuit is integrated within the memory cell array region to maintain density, while the second ECC circuit is placed outside for optimized error correction. This local differentiation allows simultaneous achievement of high density and strong error correction capability.
3Quantity of substance
If ECC circuits are integrated within the memory cell array footprint, then memory cell density is maintained, but error correction operation speed may be compromised
Solution Approach 1:
The ECC circuit functionality is distributed across different spatial dimensions and operational domains. The first ECC circuit operates within the two-dimensional memory cell array footprint for write operations, while the second ECC circuit operates in a separate domain for read operations. This dimensional separation allows speed optimization for read operations without compromising the density achieved in the memory array.
Data Source
AI summary
Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.