Error Correction/Detection By Combining Multiple Code Structures TRIZ Cases
- Stripe Consistency Verification Using CRC and EC Linear Checks
CRC blocks derived from EC transformations verify stripe consistency without converging full data blocks, cutting bandwidth and compute load.
- Dual ECC Layout for Memory Arrays Balancing Density and Read Speed
A split ECC layout places one circuit under the memory array and another outside it to preserve density while speeding read correction.
- Bus Bit Inversion Using Hamming Distance to Cut Wire Count
A bus inversion scheme flips data and parity when Hamming distance is high, reducing transitions, wire count, and power in fast links.
- Dual ECC Circuit Layout for Memory Read Speed and Cell Density
Separate ECC circuits for write and read operations preserve memory cell density while improving read speed and accuracy.
- PDCCH DCI Format Identification Using Polar Code and Distributed CRC
Distributed CRC placement and padding-bit frozen fields help UE identify DCI format earlier, cutting blind detections and decoding delay.