Dual ECC Circuit Layout for Memory Read Speed and Cell Density
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Solution Overview
Problem
Memory devices face challenges in efficiently performing error correction operations due to the space occupied by ECC circuits, which can reduce memory cell density and operational efficiency.
Innovation Solution
The implementation of a dual ECC circuit system, where a first ECC circuit is located under the memory cell array to maintain density during write operations and a second ECC circuit, positioned outside, optimizes read operations by increasing speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single ECC circuit is used for both read and write operations, then device complexity is reduced, but operational efficiency and speed for specific operations cannot be optimized
Solution Approach 1:
The ECC circuit is segmented into two separate circuits: a first ECC circuit coupled with the memory cell array for write operations, and a second ECC circuit for read operations. This segmentation allows each circuit to be independently optimized for its specific operation type, improving overall operational efficiency while maintaining manageable device complexity through functional specialization.
2Speed
If ECC circuits are placed outside the memory cell array, then read operation speed is improved, but memory cell density is reduced
Solution Approach 1:
The ECC functionality is segmented into two separate circuits with different spatial configurations: the first ECC circuit is integrated with the memory cell array to maintain density, while the second ECC circuit is positioned outside the array to optimize read operation speed. This segmentation resolves the contradiction by allowing each circuit to serve its specific purpose in the most efficient location.
3Quantity of substance
If ECC circuits are integrated under the memory cell array, then memory cell density is maintained, but read operation speed and accuracy are limited
Solution Approach 1:
The ECC system is segmented into two circuits: the first ECC circuit integrated under the memory cell array maintains high memory cell density for write operations, while the second ECC circuit positioned outside the array provides optimized read operation speed and accuracy. This dual-circuit segmentation allows simultaneous optimization of both density and read performance.
4Productivity
If a single ECC circuit handles all operations, then manufacturing simplicity is achieved, but operational speed and accuracy for specific operations cannot be optimized
Solution Approach 1:
The ECC functionality is segmented into two separately optimized circuits that can be independently designed, manufactured, and tested. The first ECC circuit is optimized for write operations with integration under the memory cell array, while the second ECC circuit is optimized for read operations with positioning outside the array. This segmentation enables operational speed optimization for each operation type while maintaining relative manufacturing simplicity through modular design.
Data Source
AI summary
Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.