Multi-Phase Dual-Edge DPWM Circuit for High-Resolution Linearity
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Solution Overview
Problem
Conventional hybrid digital pulse width modulation circuits suffer from increased area and power consumption due to exponential growth when resolution is enhanced, leading to jitter issues and compromised linearity, especially in systems requiring high time resolution and precision.
Innovation Solution
A multi-phase dual-edge digital pulse width modulation device employing a closed-loop feedback control mechanism with a dual-edge inverted delay line, utilizing a delay locked loop and phase blending circuit to reduce complexity, area, and power consumption while improving resolution and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of delay line-based digital pulse width modulation circuits is increased by adding more delay units, then the resolution is improved, but the area and power consumption grow exponentially
Solution Approach 1:
The delay line is divided into multiple phases (first phase, second phase, third phase, fourth phase) with each phase containing a subset of delay units. This segmentation allows the system to achieve high resolution through phase selection and combination rather than requiring a single long delay line, thereby reducing the total area while maintaining time resolution precision.
Solution Approach 2:
The patent transitions from a one-dimensional sequential delay line to a multi-dimensional phased structure. By organizing delay units into multiple phases that can be selectively activated, the system achieves exponential resolution improvement with linear area growth, fundamentally changing the scaling relationship between resolution and area.
2Measurement precision
If the resolution of delay line-based digital pulse width modulation circuits is increased by adding more delay units, then the resolution is improved, but the power consumption grows exponentially
Solution Approach 1:
The delay line is divided into multiple phases (first phase, second phase, third phase, fourth phase) with each phase containing a subset of delay units. This segmentation allows the system to achieve high resolution through phase selection and combination rather than requiring a single long delay line, thereby reducing the total area while maintaining time resolution precision.
Solution Approach 2:
The patent transitions from a one-dimensional sequential delay line to a multi-dimensional phased structure. By organizing delay units into multiple phases that can be selectively activated, the system achieves exponential resolution improvement with linear area growth, fundamentally changing the scaling relationship between resolution and area.
3Measurement precision
If more delay units are added to increase resolution, then the resolution is improved, but the startup time of the delay line increases
Solution Approach 1:
The delay line is divided into multiple phases (first phase, second phase, third phase, fourth phase) with each phase containing a subset of delay units. This segmentation allows the system to achieve high resolution through phase selection and combination rather than requiring a single long delay line, thereby reducing the total area while maintaining time resolution precision.
Solution Approach 2:
Multiple phases are pre-configured with their respective delay units ready for immediate activation. When high resolution is needed, the system can quickly switch between phases or combine them without requiring gradual initialization of a long sequential delay line, significantly reducing startup time while maintaining high resolution capability.
4Device complexity
If conventional hybrid digital pulse width modulation circuits are used, then the linearity is affected by PVT variations, but the circuit structure is simpler
Solution Approach 1:
A phase detector is introduced that continuously monitors the phase relationship between the input clock signal and the delayed clock signals from each phase. Based on the phase detection results, the system dynamically adjusts the activation and combination of different phases to compensate for PVT variations, thereby maintaining high linearity without requiring overly complex circuit structures.
Solution Approach 2:
The system transitions from a static delay line configuration to a dynamic phased structure where different phases can be selectively activated and combined based on real-time conditions. This dynamic adaptation allows the system to maintain optimal performance across varying PVT conditions while keeping the base circuit structure relatively simple.
Data Source
AI summary
A multi-phase dual-edge digital pulse width modulation device includes a delay locked loop, a delay locked loop logic circuit, and at least one digital pulse width modulation logic circuit. The delay locked loop receives an input clock signal and thereby sequentially generates first delayed clock signals and a second delayed clock signal. All first delayed clock signals are alternately divided into a first group and a second group. The delay locked loop generates a synchronous clock signal, first synchronous delayed clock signals, and second synchronous delayed clock signals and transmits them to the digital pulse width modulation logic circuit to generates a pulse width modulation signal in response to a control digital code. The time occupied by the high voltage level of the pulse width modulation signal is positively correlated with the value of the control digital code.