Dual-Edge Phase Error Detection for Precise PLL Lock Status
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Solution Overview
Problem
Existing clock-tracking circuits, such as phase locked loops and delay locked loops, face challenges in accurately determining a locked status due to imprecise analog control signals and imperfect representations of phase error, leading to potential errors in locked status determinations.
Innovation Solution
A locked status detector is introduced that utilizes a phase detector with a settable phase threshold and a digital discriminator to distinguish between steady-state and transitory phase errors, sampling and decoding a status signal to determine the locked status of a clock tracking circuit based on the phase difference between reference and feedback clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog control signals are used for phase error detection, then the circuit can operate continuously, but the measurement precision deteriorates due to imprecise analog signals
Solution Approach 1:
The patent replaces analog control signals with digital signals for phase error detection. The phase detector generates digital UP and DOWN signals that accurately represent phase error without the imprecision of analog signals, while the charge pump and loop filter maintain continuous operation through digital control
Solution Approach 2:
The patent introduces a digital discriminator as an intermediary component that samples and processes the digital phase error signals. This discriminator filters transitory errors and provides stable digital control to the N-divider, improving measurement precision while maintaining continuous circuit operation
2Measurement precision
If digital discriminator is added to filter transitory errors, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent segments the phase detection and control function into distinct digital components: a phase detector that generates UP/DOWN signals, a charge pump that converts these to control pulses, and a digital discriminator that samples and filters the signals. This segmentation improves precision while keeping each component relatively simple
Solution Approach 2:
The digital discriminator automatically samples the phase error signals at appropriate intervals and inherently filters transitory errors through its sampling mechanism, providing self-regulating precision improvement without requiring complex external control circuits
Data Source
AI summary
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.