Dual Edge Synchronization Reduces Analog Input Jitter
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Solution Overview
Problem
Electronic sensors that output asynchronous signals often experience jitter, which affects accuracy in detecting target position and movement, and synchronous systems face additional jitter due to non-zero clock periods, making it difficult to reduce clock period-related jitter without increasing switching current consumption or using non-ideal dual clock domains.
Innovation Solution
Implementing dual edge synchronization by allowing output on either edge of the system clock, depending on which edge occurs first after an asynchronous input from analog circuitry, using a method that provides the input signal to both a first and second signal path associated with different clocks and selecting the input signal based on detected edges to synchronize with the closest clock edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock period is reduced to reduce clock period-related jitter, then jitter is reduced, but switching current consumption increases
Solution Approach 1:
The patent applies dynamics by allowing the system to adaptively select between rising and falling clock edges based on the timing of asynchronous inputs. The edge selection logic dynamically determines which clock edge occurs first after the asynchronous input, enabling flexible synchronization without requiring a fixed clock period reduction. This resolves the contradiction by achieving jitter reduction through intelligent edge selection rather than simply reducing clock period, thereby avoiding the associated increase in switching current consumption.
Solution Approach 2:
The patent changes the parameter of clock edge selection by allowing the system to operate with either rising or falling edges of the clock signal, depending on which occurs first after the asynchronous input. This parameter change enables the system to maintain the original clock period while reducing jitter through adaptive synchronization, avoiding the need to reduce clock period and the associated energy consumption increase.
2Measurement precision
If a digital controller with two clock domains is used to reduce clock period-related jitter, then jitter is reduced, but device complexity increases due to multiple scan chains and timing issues
Solution Approach 1:
The patent merges the synchronization function into a single clock domain by using edge detection logic that operates within one domain. Instead of splitting the system into two clock domains with separate scan chains, the invention combines the asynchronous input synchronization with the existing single clock domain, eliminating the complexity of multiple scan chains and inter-domain timing issues while still achieving jitter reduction through adaptive edge selection.
Solution Approach 2:
The patent introduces an intermediary edge detection and selection logic that mediates between the asynchronous input and the synchronous output. This intermediary component, which includes edge detection circuits and selection logic, processes the asynchronous input and determines the optimal clock edge for synchronization without requiring a second clock domain. This mediator approach reduces device complexity by avoiding the need for multiple scan chains while still achieving jitter reduction.
3Measurement precision
If the clock frequency is increased to reduce clock period-related jitter, then jitter is reduced, but switching current consumption increases
Solution Approach 1:
The patent applies dynamics by allowing the system to adaptively select between rising and falling clock edges based on the timing of asynchronous inputs. The edge selection logic dynamically determines which clock edge occurs first after the asynchronous input, enabling flexible synchronization without requiring a fixed clock period reduction. This resolves the contradiction by achieving jitter reduction through intelligent edge selection rather than simply reducing clock period, thereby avoiding the associated increase in switching current consumption.
Data Source
AI summary
A method for synchronization of an input signal includes providing the input signal to a first signal path associated with a first clock and to a second signal path associated with a second clock, detecting an edge of the input signal by detecting values of the input signal along the first signal path at a first rising edge of the first clock and at a second rising edge of the first clock, detecting a value of the input signal along the second signal path at an edge of the second clock, and selecting the input signal from the first signal path or from the second signal path according to the detected value of the input signal along the second path when an edge of the input signal along the first path is detected.