Dual-Edge Systolic Array Clocking for Lower Peak Power
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Solution Overview
Problem
Clocking all systolic stages of a systolic array on the same edge of an input clock signal leads to inefficiencies, particularly increased power consumption.
Innovation Solution
Clocking a first group of systolic stages on a rising edge and a second group on a falling edge of the input clock signal, using control logic with additional clock delays to synchronize data flow and reduce peak power demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all systolic stages are clocked on the same edge of the clock signal, then the data flow is simple to control, but the peak power consumption increases
Solution Approach 1:
The systolic array is divided into multiple groups, where each group is clocked on alternating edges of the clock signal. This segmentation distributes the computational workload across different clock edges, preventing simultaneous activation of all processing elements and thereby reducing peak power consumption while maintaining manageable data flow control through structured grouping.
2Use of energy by stationary object
If systolic stages are clocked on alternating edges, then power consumption is distributed evenly, but the control logic becomes more complex
Solution Approach 1:
The control logic utilizes periodic alternating clock edges (rising and falling edges) to systematically activate different groups of systolic stages. This periodic pattern creates a predictable, rhythmic activation sequence that distributes power consumption evenly across clock cycles while the structured periodic nature simplifies the control logic compared to arbitrary activation schemes.
Data Source
AI summary
The present disclosure is directed to an apparatus that includes a systolic array having an initial systolic stage that is clocked at a first edge of a clock signal. The apparatus further includes control logic configured to clock a first subset of a plurality of additional systolic stages of the systolic array at the first edge of the clock signal. The control logic is further configured to clock a second subset of the plurality of systolic stages at a second edge of the clock signal.