Dual-Function FET Circuit for Logic and Embedded Memory Driving
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Solution Overview
Problem
Current integrated circuit (IC) fabrication methods lack a circuit architecture that efficiently combines transistors with dynamic dual functionality for both logic and embedded memory drivers, leading to increased device count and power consumption.
Innovation Solution
The implementation of a new circuit architecture using field-effect transistors (FETs) that are connected to both logic and non-volatile memory elements through bistable resistive elements, allowing the same transistors to operate in both logic and memory driver modes by switching between resistance states, thereby reducing the number of devices required and optimizing power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate transistors are used for logic and memory drivers, then circuit functionality is achieved, but device count increases and power consumption rises
Solution Approach 1:
The patent implements a single transistor that can dynamically switch between logic circuit mode and memory driver mode through control signals. The transistor serves universal purposes by being reconfigurable: when a control signal is applied to the gate, it operates as a logic element, and when the control signal is removed, it operates as a memory driver, eliminating the need for separate dedicated transistors for each function.
Solution Approach 2:
The transistor's functionality is made dynamic rather than static. The circuit architecture allows the transistor to change its operational role in real-time based on control signals. This dynamic reconfiguration enables the same physical transistor to adapt its behavior and connectivity to serve different circuit functions as needed, reducing the overall device count while maintaining full functionality.
2Adaptability or versatility
If separate transistors are used for logic and memory drivers, then circuit functionality is achieved, but power consumption increases
Solution Approach 1:
By making the transistor universal and reconfigurable, the patent eliminates redundant transistors that would otherwise be needed for both logic and memory driver functions. Fewer transistors mean fewer active components consuming power, thereby reducing overall power consumption while maintaining the ability to perform both logic operations and memory driving functions.
Solution Approach 2:
The patent merges the functions of separate logic transistors and memory driver transistors into a single reconfigurable transistor. This consolidation reduces the total number of active devices in the circuit, directly lowering dynamic power consumption associated with charging and discharging multiple transistor gates and associated parasitic capacitances.
3Adaptability or versatility
If more devices are used to ensure both logic and memory driver functions, then functionality is improved, but circuit compactness deteriorates
Solution Approach 1:
The reconfigurable transistor architecture allows a single transistor to fulfill multiple functional roles (logic and memory driver), thereby reducing the total number of devices required on the chip. This directly decreases the chip area needed while preserving complete circuit functionality across both logic and memory operations.
Solution Approach 2:
By merging separate logic and memory driver transistor functions into one unified reconfigurable device, the patent reduces the spatial footprint of the circuit. The same physical transistor can be dynamically assigned to different functional roles, maximizing area utilization and enabling more compact IC design.
Data Source
AI summary
Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.