Dual Fin Integration for Electron and Hole Mobility
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Solution Overview
Problem
In integrated circuit manufacturing, existing technologies face challenges in enhancing both electron and hole mobility simultaneously, which is crucial for improving transistor performance and reducing leakage current, as advanced geometry planar FETs suffer from source and drain encroachment into the channel, leading to difficulty in turning transistors completely off.
Innovation Solution
A dual fin integration method is employed, where trapezoidal shaped fins are formed to enhance electron mobility and vertical shaped fins are formed to enhance hole mobility, with the trapezoidal fins having a larger base than the vertical fins, both integrated into a semiconductor device to optimize carrier mobility in FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced geometry planar FETs are used, then device performance is improved, but source and drain encroachment into the channel occurs, making it difficult to turn transistors completely off
Solution Approach 1:
The invention segments the fin structure into two distinct types: vertical fins for hole mobility enhancement and trapezoidal fins for electron mobility enhancement. This segmentation allows each fin type to be optimized independently for its specific carrier type, resolving the contradiction by providing dedicated structures that prevent carrier leakage while maintaining high mobility for the intended carrier type.
Solution Approach 2:
The invention applies local quality by creating different fin geometries in different locations within the semiconductor device. Vertical fins are strategically placed where hole mobility enhancement is needed, while trapezoidal fins are positioned where electron mobility enhancement is required. This localized optimization ensures that each region has the appropriate structure to prevent leakage while enhancing performance for its specific carrier type.
2Ease of manufacture
If single fin structure is used, then manufacturing process is simple, but both electron and hole mobility cannot be enhanced simultaneously
Solution Approach 1:
The manufacturing process is segmented into separate etching steps for vertical fins and trapezoidal fins. The first etching process forms vertical fins using a first mandrel structure, while the second etching process forms trapezoidal fins using a second mandrel structure. This segmentation allows each fin type to be manufactured with optimized parameters while maintaining overall process feasibility.
Solution Approach 2:
The invention adds dimensional complexity by introducing two different fin geometries (vertical and trapezoidal) instead of a single fin type. This dimensional change in the fin structure allows simultaneous enhancement of both electron and hole mobility, trading increased manufacturing complexity for improved device performance.
3Reliability
If higher mobility is achieved, then device performance is improved, but device complexity increases
Solution Approach 1:
The invention reduces overall device complexity by applying local quality principles - each fin type is optimized locally for its specific carrier type rather than attempting to create a single complex structure that handles both carriers. This localized optimization simplifies the design space while achieving high mobility for both electrons and holes.
Solution Approach 2:
The device is segmented into distinct regions with different fin types, allowing independent optimization of electron and hole transport paths. This segmentation prevents the need for a single overly complex structure and enables simpler, more effective fin designs for each carrier type.
Data Source
AI summary
A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.